A logic-to-logic comparator for VLSI layout verification.
Peter M. MaurerAlexander D. SchapiraPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (1988)
Keyphrases
- classical logic
- logic programming
- asynchronous circuits
- bounded model checking
- predicate logic
- sound and complete axiomatization
- multi agent systems
- high speed
- signal processing
- modal logic
- multi valued
- digital circuits
- computational properties
- verification method
- deontic logic
- epistemic logic
- nonmonotonic logics
- set theory
- database
- computer vision
- real time