Login / Signup
Peng Chen
ORCID
Publication Activity (10 Years)
Years Active: 2015-2023
Publications (10 Years): 14
Top Topics
Low Power
Top Venues
IEEE Trans. Circuits Syst. I Regul. Pap.
IEEE J. Solid State Circuits
A-SSCC
EBCCSP
</>
Publications
</>
Zhong Gao
,
Jingchu He
,
Martin Fritz
,
Jiang Gong
,
Yiyu Shen
,
Zhirui Zong
,
Peng Chen
,
Gerd Spalink
,
Ben Eitel
,
Morteza S. Alavi
,
Robert Bogdan Staszewski
,
Masoud Babaie
A Low-Spur Fractional-N PLL Based on a Time-Mode Arithmetic Unit.
IEEE J. Solid State Circuits
58 (6) (2023)
Xi Meng
,
Haoran Li
,
Peng Chen
,
Jun Yin
,
Pui-In Mak
,
Rui Paulo Martins
Analysis and Design of a 15.2-to-18.2-GHz Inverse-Class-F VCO With a Balanced Dual-Core Topology Suppressing the Flicker Noise Upconversion.
IEEE Trans. Circuits Syst. I Regul. Pap.
70 (12) (2023)
Peng Chen
,
Jun Yin
,
Feifei Zhang
,
Pui-In Mak
,
Rui Paulo Martins
,
Robert Bogdan Staszewski
Mismatch Analysis of DTCs With an Improved BIST-TDC in 28-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap.
69 (1) (2022)
Peng Chen
,
Xi Meng
,
Jun Yin
,
Pui-In Mak
,
Rui Paulo Martins
,
Robert Bogdan Staszewski
A 529-μW Fractional-N All-Digital PLL Using TDC Gain Auto-Calibration and an Inverse-Class-F DCO in 65-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap.
69 (1) (2022)
Zhong Gao
,
Jingchu He
,
Martin Fritz
,
Jiang Gong
,
Yiyu Shen
,
Zhirui Zong
,
Peng Chen
,
Gerd Spalink
,
Ben Eitel
,
Ken Yamamoto
,
Robert Bogdan Staszewski
,
Morteza S. Alavi
,
Masoud Babaie
A 2.6-to-4.1GHz Fractional-N Digital PLL Based on a Time-Mode Arithmetic Unit Achieving -249.4dB FoM and -59dBc Fractional Spurs.
ISSCC
(2022)
Feifei Zhang
,
Peng Chen
,
Jeffrey S. Walling
,
Anding Zhu
,
Robert Bogdan Staszewski
An Active-Under-Coil RFDAC With Analog Linear Interpolation in 28-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap.
68 (5) (2021)
Suoping Hu
,
Peng Chen
,
Philip Quinlan
,
Robert Bogdan Staszewski
A 0.7-V Sub-mW Type-II Phase-Tracking Bluetooth Low Energy Receiver in 28-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap.
68 (6) (2021)
Suoping Hu
,
Jianglin Du
,
Peng Chen
,
Hieu Minh Nguyen
,
Philip Quinlan
,
Teerachot Siriburanon
,
Robert Bogdan Staszewski
A Type-II Phase-Tracking Receiver.
IEEE J. Solid State Circuits
56 (2) (2021)
Peng Chen
,
Feifei Zhang
,
Suoping Hu
,
Robert Bogdan Staszewski
A Feedforward and Feedback Constant-Slope Digital-to-Time Converter in 28nm CMOS Achieving ≤ 0.12% INL/Range over >100mV Supply Range.
VLSI Circuits
(2021)
Zhirui Zong
,
Peng Chen
,
Robert Bogdan Staszewski
A Low-Noise Fractional- ${N}$ Digital Frequency Synthesizer With Implicit Frequency Tripling for mm-Wave Applications.
IEEE J. Solid State Circuits
54 (3) (2019)
Peng Chen
,
Feifei Zhang
,
Zhirui Zong
,
Suoping Hu
,
Teerachot Siriburanon
,
Robert Bogdan Staszewski
A 31-µW, 148-fs Step, 9-bit Capacitor-DAC-Based Constant-Slope Digital-to-Time Converter in 28-nm CMOS.
IEEE J. Solid State Circuits
54 (11) (2019)
Peng Chen
,
Xiongchuan Huang
,
Yue Chen
,
Lianbo Wu
,
Robert Bogdan Staszewski
An On-Chip Self-Characterization of a Digital-to-Time Converter by Embedding it in a First-Order ΔΣ Loop.
IEEE Trans. Circuits Syst. I Regul. Pap.
(11) (2018)
Peng Chen
,
Feifei Zhang
,
Zhirui Zong
,
Hao Zheng
,
Teerachot Siriburanon
,
Robert Bogdan Staszewski
A 15-μW, 103-fs step, 5-bit capacitor-DAC-based constant-slope digital-to-time converter in 28nm CMOS.
A-SSCC
(2017)
Peng Chen
,
Robert Bogdan Staszewski
Exponential extended flash time-to-digital converter.
EBCCSP
(2016)
Peng Chen
,
Xiongchuan Huang
,
Yao-Hong Liu
,
Ming Ding
,
Cui Zhou
,
Ao Ba
,
Kathleen Philips
,
Harmke de Groot
,
Robert Bogdan Staszewski
Design and built-in characterization of digital-to-time converters for ultra-low power ADPLLs.
ESSCIRC
(2015)
Peng Chen
,
Xiongchuan Huang
,
Robert Bogdan Staszewski
Fractional spur suppression in all-digital phase-locked loops.
ISCAS
(2015)