Jianglin Du

Publication Activity (10 Years)

Years Active: 2019-2023
Publications (10 Years): 11

Top Topics

Phase Locked Loop

Noise Reduction

Top Venues

IEEE J. Solid State Circuits

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Xi Chen, Yizhe Hu, Teerachot Siriburanon, Jianglin Du, Robert Bogdan Staszewski, Anding Zhu
A 30-GHz Class-F Quadrature DCO Using Phase Shifts Between Drain-Gate-Source for Low Flicker Phase Noise and I/Q Exactness. IEEE J. Solid State Circuits 58 (7) (2023)
Yizhe Hu, Xi Chen, Teerachot Siriburanon, Jianglin Du, Vivek Govindaraj, Anding Zhu, Robert Bogdan Staszewski
A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking. IEEE J. Solid State Circuits 57 (2) (2022)
Jianglin Du, Yizhe Hu, Teerachot Siriburanon, Enis Kobal, Philip Quinlan, Anding Zhu, Robert Bogdan Staszewski
Noise Over Wide Tuning Range. IEEE J. Solid State Circuits 57 (2) (2022)
Xi Chen, Yizhe Hu, Teerachot Siriburanon, Jianglin Du, Robert Bogdan Staszewski, Anding Zhu
Flicker Phase-Noise Reduction Using Gate-Drain Phase Shift in Transformer-Based Oscillators. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (3) (2022)
Jianglin Du, Teerachot Siriburanon, Yizhe Hu, Vivek Govindaraj, Robert Bogdan Staszewski
A Reference-Waveform Oversampling Technique in a Fractional-N ADPLL. IEEE J. Solid State Circuits 56 (11) (2021)
Suoping Hu, Jianglin Du, Peng Chen, Hieu Minh Nguyen, Philip Quinlan, Teerachot Siriburanon, Robert Bogdan Staszewski
A Type-II Phase-Tracking Receiver. IEEE J. Solid State Circuits 56 (2) (2021)
Jianglin Du, Teerachot Siriburanon, Xi Chen, Yizhe Hu, Vivek Govindaraj, Anding Zhu, Robert Bogdan Staszewski
A 24-31 GHz Reference Oversampling ADPLL Achieving FoMjitter-N of -269.3 dB. VLSI Circuits (2021)
Ali Esmailiyan, Jianglin Du, Teerachot Siriburanon, Filippo Schembari, Robert Bogdan Staszewski
Dickson-Charge-Pump-Based Voltage-to-Time Conversion for Time-Based ADCs in 28-nm CMOS. IEEE Open J. Circuits Syst. 2 (2021)
Yizhe Hu, Xi Chen, Teerachot Siriburanon, Jianglin Du, Zhong Gao, Vivek Govindaraj, Anding Zhu, Robert Bogdan Staszewski
17.6 A 21.7-to-26.5GHz Charge-Sharing Locking Quadrature PLL with Implicit Digital Frequency-Tracking Loop Achieving 75fs Jitter and -250dB FoM. ISSCC (2020)
Jianglin Du, Yizhe Hu, Teerachot Siriburanon, Robert Bogdan Staszewski
-Corner Digitally Controlled Oscillator with Vertically Integrated Switched Capacitor Banks Achieving FoMT of -199dB in 28-nm CMOS. CICC (2019)
Vivek Govindaraj, Jianglin Du, Yizhe Hu, Teerachot Siriburanon, Robert Bogdan Staszewski
DTC-Assisted All-Digital Phase-Locked Loop Exploiting Hybrid Time/Voltage Phase Digitization. APCCAS (2019)