Partha Sharathi Mallick

Publication Activity (10 Years)

Years Active: 2012-2020
Publications (10 Years): 10

Top Topics

Error Compensation

Compressive Sensing

Top Venues

J. Circuits Syst. Comput.

Int. J. Comput. Aided Eng. Technol.

Publications

Piratla Uma Sathyakam, Partha Sharathi Mallick, Paridhi Singh
Geometry-Based Crosstalk Reduction in CNT Interconnects. J. Circuits Syst. Comput. 29 (6) (2020)
Piratla Uma Sathyakam, Partha Sharathi Mallick, Anmol Ajay Saxena
High-speed sub-threshold operation of carbon nanotube interconnects. IET Circuits Devices Syst. 13 (4) (2019)
Annasamy Bagubali, V. Prithiviraj, Partha Sharathi Mallick
Review on IMS-4G-cloud networks maintaining service continuity using distributed multi agent scheme. Int. J. Comput. Aided Eng. Technol. 10 (5) (2018)
Rajesh Ramanathan, Partha Sharathi Mallick, Thiruvengadam Sundarajan Jayaraman
Low Complexity Compressive Sensing Greedy Detection of Generalized Quadrature Spatial Modulation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (3) (2018)
R. Marimuthu, S. Balamurugan, Partha Sharathi Mallick
Design of 5-3 multicolumn compressor for high performance multiplier. Int. J. Comput. Aided Eng. Technol. 10 (5) (2018)
Annasamy Bagubali, Tanmay Verma, Anurag Anand, V. Prithiviraj, Partha Sharathi Mallick
Performance Analysis of Handover Schemes in Heterogeneous Networks. J. Circuits Syst. Comput. 27 (11) (2018)
Rajesh Ramanathan, Velmurugan Periakarupan Gurusamy Sivabalan, Thiruvengadam Sundarajan Jayaraman, Partha Sharathi Mallick
Spatial modulation and physical layer network coding based bidirectional relay network with transmit antenna selection over Nakagami-m fading channels. Int. J. Commun. Syst. 31 (14) (2018)
R. Marimuthu, Y. Elsie Rezinold, Partha Sharathi Mallick
Design and Analysis of Multiplier Using Approximate 15-4 Compressor. IEEE Access 5 (2017)
S. Balamurugan, Partha Sharathi Mallick
Error Compensation Techniques for Fixed-Width Array Multiplier Design - A Technical Survey. J. Circuits Syst. Comput. 26 (3) (2017)
Rajesh Ramanathan, Velmurugan Periakarupan Gurusamy Sivabalan, Thiruvengadam Sundarajan Jayaraman, Partha Sharathi Mallick
Outage performance of bidirectional full duplex AF relay network with joint antenna and relay selection in Nakagami-m fading environment. COMSNETS (2016)
S. Balaji, R. Santhakumar, Partha Sharathi Mallick
Enhancing Coverage and Rate of Cell Edge User in Multi-Antenna Poisson Voronoi Cells. J. Circuits Syst. Comput. 24 (8) (2015)
S. Sivanantham, M. Padmavathy, Ganga Gopakumar, Partha Sharathi Mallick, J. Raja Paul Perinbam
Enhancement of test data compression with multistage encoding. Integr. 47 (4) (2014)
S. Sivanantham, Partha Sharathi Mallick, J. Raja Paul Perinbam
Low-power selective pattern compression for scan-based test applications. Comput. Electr. Eng. 40 (4) (2014)
Piratla Uma Sathyakam, Partha Sharathi Mallick
Towards realisation of mixed carbon nanotube bundles as VLSI interconnects: A review. Nano Commun. Networks 3 (3) (2012)
S. Sivanantham, K. Sarathkumar, Jincy P. Manuel, Partha Sharathi Mallick, J. Raja Paul Perinbam
CSP-Filling: A New X-Filling Technique to Reduce Capture and Shift Power in Test Applications. ISED (2012)
S. Balamurugan, Sneha Ghosh, Atul, Balakumaran Srirangaswamy, R. Marimuthu, Partha Sharathi Mallick
Design of low power fixed-width multiplier with row bypassing. IEICE Electron. Express 9 (20) (2012)
S. Balamurugan, Balakumaran Srirangaswamy, R. Marimuthu, Partha Sharathi Mallick
FPGA design and implementation of truncated multipliers using bypassing technique. ICACCI (2012)