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R. Marimuthu
ORCID
Publication Activity (10 Years)
Years Active: 2012-2018
Publications (10 Years): 5
Top Topics
Design Process
Fpga Device
High Speed
Discrete Cosine Transform
Top Venues
SocProS (2)
IEICE Electron. Express
Int. J. Comput. Aided Eng. Technol.
VDAT
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Publications
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Shantanu Agarwal
,
G. Harish
,
S. Balamurugan
,
R. Marimuthu
Design of High Speed 5: 2 and 7: 2 Compressor Using Nanomagnetic Logic.
VDAT
(2018)
R. Marimuthu
,
S. Balamurugan
,
Partha Sharathi Mallick
Design of 5-3 multicolumn compressor for high performance multiplier.
Int. J. Comput. Aided Eng. Technol.
10 (5) (2018)
Saurabh Kumar
,
R. Marimuthu
,
S. Balamurugan
Design and Analysis of 4-Bit Squarer Circuit Using Minority and Majority Logic in MagCAD.
SocProS (2)
(2018)
Raunak R. Lahoti
,
Shantanu Agarwal
,
S. Balamurugan
,
R. Marimuthu
Realization of 2-D DCT Using Adder Compressor.
SocProS (2)
(2018)
R. Marimuthu
,
Y. Elsie Rezinold
,
Partha Sharathi Mallick
Design and Analysis of Multiplier Using Approximate 15-4 Compressor.
IEEE Access
5 (2017)
S. Balamurugan
,
Sneha Ghosh
,
Atul
,
Balakumaran Srirangaswamy
,
R. Marimuthu
,
Partha Sharathi Mallick
Design of low power fixed-width multiplier with row bypassing.
IEICE Electron. Express
9 (20) (2012)
S. Balamurugan
,
Balakumaran Srirangaswamy
,
R. Marimuthu
,
Partha Sharathi Mallick
FPGA design and implementation of truncated multipliers using bypassing technique.
ICACCI
(2012)