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Design of low power fixed-width multiplier with row bypassing.
S. Balamurugan
Sneha Ghosh
Atul
Balakumaran Srirangaswamy
R. Marimuthu
Partha Sharathi Mallick
Published in:
IEICE Electron. Express (2012)
Keyphrases
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low power
single chip
power consumption
high speed
low power consumption
low cost
gate array
logic circuits
vlsi architecture
real time
digital signal processing
nm technology
high power
mixed signal
data sets
cmos technology
design methodology
energy dissipation
ultra low power