Low-power selective pattern compression for scan-based test applications.
S. SivananthamPartha Sharathi MallickJ. Raja Paul PerinbamPublished in: Comput. Electr. Eng. (2014)
Keyphrases
- low power
- power consumption
- low cost
- high speed
- high power
- single chip
- digital signal processing
- compression ratio
- image sensor
- vlsi architecture
- image compression
- low power consumption
- wireless transmission
- cmos technology
- mixed signal
- compression algorithm
- pattern matching
- power reduction
- ultra low power
- gate array
- vlsi circuits
- power dissipation