Pallavi Paliwal

Publication Activity (10 Years)

Years Active: 2012-2023
Publications (10 Years): 7

Top Topics

Stability Analysis

Top Venues

IEEE Control. Syst. Lett.

Publications

Zeeshan Ali, Pallavi Paliwal, Phani Raj, Deepak Anand, Debasattam Pal, Shalabh Gupta
Stability Analysis for Fast Settling Switched Digital Phase-Locked Loops (DPLLs). IEEE Control. Syst. Lett. 7 (2023)
Zeeshan Ali, Pallavi Paliwal, Rupesh Lad, Dhanraj Bhukya, Shalabh Gupta
A Fast Locking Ring Oscillator Based Fractional-N DPLL With an Assistance From a LUT-Based FSM. ISCAS (2022)
Pallavi Paliwal, Vivek Yadav, Zeeshan Ali, Shalabh Gupta
A Fast Settling Fractional-N DPLL With Loop-Order Switching. IEEE Trans. Very Large Scale Integr. Syst. 28 (3) (2020)
Arun Goyal, Souvik Ghosh, Sandeep Goyal, Pallavi Paliwal, Shalabh Gupta
A High-Resolution Digital Phase Interpolator Based CDR with a Half-Rate Hybrid Phase Detector. ISCAS (2019)
Pallavi Paliwal, Debasattam Pal, Shalabh Gupta
Stability Analysis for Fast Settling Switched DPLL. CoRR (2018)
Pallavi Paliwal, Jaydip Fadadu, Anil Chawda, Shalabh Gupta
A Fast Settling 4.7-5 GHz Fractional-N Digital Phase Locked Loop. VLSI Design (2016)
Harishankar Sahu, Pallavi Paliwal, Vivek Yadav, Shalabh Gupta
A low-jitter digital-to-time converter with look-ahead multi-phase DDS. LASCAS (2016)
Anil Chawda, Pallavi Paliwal, Priyank Laad, Shalabh Gupta
High resolution digital-to-time converter for low jitter digital PLLs. ICECS (2014)
Pallavi Paliwal, Priyank Laad, Mohanrao Sattineni, Shalabh Gupta
Tradeoffs between settling time and jitter in phase locked loops. MWSCAS (2013)
Angada B. Sachid, Pallavi Paliwal, S. Joshi, Maryam Shojaei Baghini, Dinesh Sharma, V. Ramgopal Rao
Circuit Optimization at 22nm Technology Node. VLSI Design (2012)