Naoya Torii

Publication Activity (10 Years)

Years Active: 1999-2022
Publications (10 Years): 8

Top Topics

Biometric Authentication

Experimental Evaluation

Reverse Engineer

Top Venues

IACR Cryptol. ePrint Arch.

Publications

Kotaro Hayashi, Ryuichi Minagawa, Naoya Torii
Side-channel attack on COSO-based TRNG to estimate output bits. CANDARW (2022)
Naoya Torii, Ryuichi Minagawa, Hideaki Kevin Omae, Kotaro Hayashi
Implementation and Evaluation of Ring Oscillator-based True Random Number Generator. Int. J. Netw. Comput. 12 (2) (2022)
Naoya Torii, Ryuichi Minagawa, Hideaki Kevin Omae, Kotaro Hayashi
Implementation and Evaluation of Ring Oscillator-based True Random Number Generator. CANDAR (2021)
Naoya Torii, Dai Yamamoto, Tsutomu Matsumoto
Evaluation of Latch-based Physical Random Number Generator Implementation on 40 nm ASICs. TrustED@CCS (2016)
Naoya Torii, Hirotaka Kokubo, Dai Yamamoto, Kouichi Itoh, Masahiko Takenaka, Tsutomu Matsumoto
ASIC implementation of random number generators using SR latches and its evaluation. EURASIP J. Inf. Secur. 2016 (2016)
Naoya Torii, Dai Yamamoto, Tsutomu Matsumoto
Evaluation of Latch-Based PUFs Implemented on 40 nm ASICs. CANDAR (2016)
Naoya Torii, Dai Yamamoto, Masahiko Takenaka, Tsutomu Matsumoto
Experimental Evaluation on the Resistance of Latch PUFs Implemented on ASIC against FIB-Based Invasive Attacks. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (1) (2016)
Dai Yamamoto, Kazuo Sakiyama, Mitsugu Iwamoto, Kazuo Ohta, Masahiko Takenaka, Kouichi Itoh, Naoya Torii
A new method for enhancing variety and maintaining reliability of PUF responses and its evaluation on ASICs. J. Cryptogr. Eng. 5 (3) (2015)
Dai Yamamoto, Masahiko Takenaka, Kazuo Sakiyama, Naoya Torii
A Technique Using PUFs for Protecting Circuit Layout Designs against Reverse Engineering. IWSEC (2014)
Dai Yamamoto, Masahiko Takenaka, Kazuo Sakiyama, Naoya Torii
Security Evaluation of Bistable Ring PUFs on FPGAs using Differential and Linear Analysis. FedCSIS (2014)
Naoya Torii, Dai Yamamoto, Masahiko Takenaka, Tsutomu Matsumoto
Dynamic Behavior of RS latches using FIB processing and probe connection. IACR Cryptol. ePrint Arch. 2014 (2014)
Tetsuya Izu, Yumi Sakemi, Masahiko Takenaka, Naoya Torii
A Spoofing Attack against a Cancelable Biometric Authentication Scheme. AINA (2014)
Hirotaka Kokubo, Dai Yamamoto, Masahiko Takenaka, Kouichi Itoh, Naoya Torii
Evaluation of ASIC Implementation of Physical Random Number Generators Using RS Latches. CARDIS (2013)
Naoya Torii
Foreword. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (1) (2012)
Shoichi Masui, Kenji Mukaida, Masahiko Takenaka, Naoya Torii
Design Optimization of a High-Speed, Area-Efficient and Low-Power Montgomery Modular Multiplier for RSA Algorithm. IEICE Trans. Electron. (4) (2005)
Kouichi Itoh, Jun Yajima, Masahiko Takenaka, Naoya Torii
DPA Countermeasures by Improving the Window Method. CHES (2002)
Takeshi Shimoyama, Hitoshi Yanami, Kazuhiro Yokoyama, Masahiko Takenaka, Kouichi Itoh, Jun Yajima, Naoya Torii, Hidema Tanaka
The Block Cipher SC2000. FSE (2001)
Kouichi Itoh, Masahiko Takenaka, Naoya Torii
DPA Countermeasure Based on the "Masking Method". ICISC (2001)
Souichi Okada, Naoya Torii, Kouichi Itoh, Masahiko Takenaka
) on an FPGA. CHES (2000)
Kouichi Itoh, Masahiko Takenaka, Naoya Torii, Syouji Temma, Yasushi Kurihara
Fast Implementation of Public-Key Cryptography ona DSP TMS320C6201. CHES (1999)