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Design Optimization of a High-Speed, Area-Efficient and Low-Power Montgomery Modular Multiplier for RSA Algorithm.

Shoichi MasuiKenji MukaidaMasahiko TakenakaNaoya Torii
Published in: IEICE Trans. Electron. (2005)
Keyphrases
  • low power
  • high speed
  • power consumption
  • computational complexity
  • low cost
  • vlsi architecture
  • image processing algorithms
  • single chip
  • fpga implementation
  • real time
  • smart card
  • hardware implementation