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Evaluation of Latch-based Physical Random Number Generator Implementation on 40 nm ASICs.
Naoya Torii
Dai Yamamoto
Tsutomu Matsumoto
Published in:
TrustED@CCS (2016)
Keyphrases
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random number generator
neural network
efficient implementation
low power
random number
databases
information systems
case study
object oriented
low cost
embedded systems
evaluation method
evaluation criteria
cmos technology