Mohamed Hassan

Publication Activity (10 Years)

Years Active: 2015-2024
Publications (10 Years): 30

Top Topics

Embedded Systems

Implementation Details

Comparative Study

Top Venues

ACM Trans. Embed. Comput. Syst.

Publications

Safin Bayes, Mohamed Hossam, Mohamed Hassan
Shared Data Kills Real-Time Cache Analysis. How to Resurrect It? DATE (2024)
Roger Pujol, Mohamed Hassan, Hamid Tabani, Jaume Abella, Francisco Javier Cazorla-Almeida
Tracking Coherence-Related Contention Delays in Real-Time Multicore Systems. SAC (2023)
Asier Fernández de Lecea, Mohamed Hassan, Enrico Mezzetti, Jaume Abella, Francisco J. Cazorla
Improving Timing-Related Guarantees for Main Memory in Multicore Critical Embedded Systems. RTSS (2023)
Shorouk Abdelhalim, Danesh Germchi, Mohamed Hossam, Rodolfo Pellizzoni, Mohamed Hassan
A Tight Holistic Memory Latency Bound Through Coordinated Management of Memory Resources. ECRTS (2023)
Mohamed Hassan
DISCO: Time-Compositional Cache Coherence for Multi-Core Real-Time Embedded Systems. IEEE Trans. Computers 72 (4) (2023)
Bailian Sun, Safin Bayes, Abdelrhman Mohamed Abotaleb, Mohamed Hassan
The Case for tinyML in Healthcare: CNNs for Real-Time On-Edge Blood Pressure Estimation. SAC (2023)
Reza Mirosanlou, Mohamed Hassan, Rodolfo Pellizzoni
Parallelism-Aware High-Performance Cache Coherence with Tight Latency Bounds. ECRTS (2022)
Reza Mirosanlou, Mohamed Hassan, Rodolfo Pellizzoni
DuoMC: Tight DRAM Latency Bounds with Shared Banks and Near-COTS Performance. MEMSYS (2021)
Anirudh Mohan Kaushik, Mohamed Hassan, Hiren D. Patel
Designing Predictable Cache Coherence Protocols for Multi-Core Real-Time Systems. IEEE Trans. Computers 70 (12) (2021)
Reza Mirosanlou, Mohamed Hassan, Rodolfo Pellizzoni
Duetto: Latency Guarantees at Minimal Performance Cost. DATE (2021)
Mohamed Hassan
Discriminative Coherence: Balancing Performance and Latency Bounds in Data-Sharing Multi-Core Real-Time Systems. ECRTS (2020)
Reza Mirosanlou, Mohamed Hassan, Rodolfo Pellizzoni
DRAMbulism: Balancing Performance and Predictability through Dynamic Pipelining. RTAS (2020)
Mohamed Hassan
Reduced latency DRAM for multi-core safety-critical real-time systems. Real Time Syst. 56 (2) (2020)
Mohamed Hassan, Rodolfo Pellizzoni
Analysis of Memory-Contention in Heterogeneous COTS MPSoCs. ECRTS (2020)
Reza Mirosanlou, Danlu Guo, Mohamed Hassan, Rodolfo Pellizzoni
MCsim: An Extensible DRAM Memory Controller Simulator. IEEE Comput. Archit. Lett. 19 (2) (2020)
Mohamed Hassan
Managing DRAM Interference in Mixed Criticality Embedded Systems. ICM (2019)
Nivedita Sritharan, Anirudh M. Kaushik, Mohamed Hassan, Hiren D. Patel
Enabling Predictable, Simultaneous and Coherent Data Sharing in Mixed Criticality Systems. RTSS (2019)
Mohamed Hassan, Rodolfo Pellizzoni
Bounding DRAM Interference in COTS Heterogeneous MPSoCs for Mixed Criticality Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (11) (2018)
Mohamed Hassan
On the Off-Chip Memory Latency of Real-Time Systems: Is DDR DRAM Really the Best Option? RTSS (2018)
Mohamed Hassan
Heterogeneous MPSoCs for Mixed-Criticality Systems: Challenges and Opportunities. IEEE Des. Test 35 (4) (2018)
Mohamed Hassan, Anirudh M. Kaushik, Hiren D. Patel
Exposing Implementation Details of Embedded DRAM Memory Controllers through Latency-based Analysis. ACM Trans. Embed. Comput. Syst. 17 (5) (2018)
Mohamed Hassan, Hiren D. Patel
MCXplore: Automating the Validation Process of DRAM Memory Controller Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (5) (2018)
Mohamed Hassan
On the Off-chip Memory Latency of Real-Time Systems: Is DDR DRAM Really the Best Option? CoRR (2018)
Danlu Guo, Mohamed Hassan, Rodolfo Pellizzoni, Hiren D. Patel
A Comparative Study of Predictable DRAM Controllers. ACM Trans. Embed. Comput. Syst. 17 (2) (2018)
Mohamed Hassan, Hiren D. Patel, Rodolfo Pellizzoni
PMC: A Requirement-Aware DRAM Controller for Multicore Mixed Criticality Systems. ACM Trans. Embed. Comput. Syst. 16 (4) (2017)
Mohamed Hassan, Anirudh M. Kaushik, Hiren D. Patel
Predictable Cache Coherence for Multi-core Real-Time Systems. RTAS (2017)
Nivedita Sritharan, Anirudh M. Kaushik, Mohamed Hassan, Hiren D. Patel
HourGlass: Predictable Time-based Cache Coherence Protocol for Dual-Critical Multi-Core Systems. CoRR (2017)
Mohamed Hassan
Heterogeneous MPSoCs for Mixed Criticality Systems: Challenges and Opportunities. CoRR (2017)
Mohamed Hassan, Hiren D. Patel
Criticality- and Requirement-Aware Bus Arbitration for Multi-Core Mixed Criticality Systems. RTAS (2016)
Mohamed Hassan, Hiren D. Patel
MCXplore: An automated framework for validating memory controller designs. DATE (2016)
Mohamed Hassan, Hiren D. Patel, Rodolfo Pellizzoni
A framework for scheduling DRAM memory accesses for multi-core mixed-time critical systems. RTAS (2015)
Mohamed Hassan, Anirudh M. Kaushik, Hiren D. Patel
Reverse-engineering embedded memory controllers through latency-based analysis. RTAS (2015)