DuoMC: Tight DRAM Latency Bounds with Shared Banks and Near-COTS Performance.

Reza Mirosanlou Mohamed Hassan Rodolfo Pellizzoni

Published in: MEMSYS (2021)

Keyphrases

lower bound
upper bound
worst case
generalization error bounds
third party
main memory
high density
lower and upper bounds
upper and lower bounds
decision support
limited resources
multi dimensional
error bounds
prefetching
response time
low latency
input output
high speed
bandwidth consumption
information technology