Mitrajit Chatterjee

Publication Activity (10 Years)

Years Active: 1993-2003
Publications (10 Years): 0

Publications

Mitrajit Chatterjee, Dhiraj K. Pradhan
A BIST Pattern Generator Design for Near-Perfect Fault Coverage. IEEE Trans. Computers 52 (12) (2003)
Mitrajit Chatterjee, Savita Banerjee, Dhiraj K. Pradhan
Buffer Assignment Algorithms on Data Driven ASICs. IEEE Trans. Computers 49 (1) (2000)
Debjyoti Paul, Mitrajit Chatterjee, Dhiraj K. Pradhan
VERILAT: verification using logic augmentation and transformations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19 (9) (2000)
Dhiraj K. Pradhan, Mitrajit Chatterjee
GLFSR-a new test pattern generator for built-in-self-test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (2) (1999)
Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang Kunz
LOT: Logic Optimization with Testability. New transformations for logic synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17 (5) (1998)
Dhiraj K. Pradhan, Debjyoti Paul, Mitrajit Chatterjee
VERILAT: verification using logic augmentation and transformations. ICCAD (1996)
Dhiraj K. Pradhan, Mitrajit Chatterjee, Madhu V. Swarna, Wolfgang Kunz
Gate-level synthesis for low-power using new transformations. ISLPED (1996)
Barun K. Kar, Mitrajit Chatterjee, Dhiraj K. Pradhan
BIT-based weighted mean filter. EUSIPCO (1996)
Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang Kunz
LOT: logic optimization with testability-new transformations using recursive learning. ICCAD (1995)
Mitrajit Chatterjee, Dhiraj K. Pradhan
A novel pattern generator for near-perfect fault-coverage. VTS (1995)
Dhiraj K. Pradhan, Mitrajit Chatterjee
GLFSR - A New Test Pattern Generator for Built-In Self-Test. ITC (1994)
Dhiraj K. Pradhan, Mitrajit Chatterjee, Savita Banerjee
Buffer assignment for data driven architectures. ICCAD (1993)