VERILAT: verification using logic augmentation and transformations.
Debjyoti PaulMitrajit ChatterjeeDhiraj K. PradhanPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2000)
Keyphrases
- asynchronous circuits
- verification method
- model checking
- bounded model checking
- model checker
- logic programming
- formal verification
- real time
- modal logic
- logical framework
- neural network
- linear temporal logic
- formal theory
- predicate logic
- classical logic
- automated reasoning
- image sequences
- case study
- signature verification
- image transformations
- defeasible logic
- digital circuits
- formal analysis
- formal methods
- deontic logic
- temporal logic
- web services
- linear time temporal logic