Mei-Fang Chiang

Publication Activity (10 Years)

Years Active: 2006-2014
Publications (10 Years): 0

Top Topics

Highly Parallel

Parallel Processing

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Yiqun Wang, Yongpan Liu, Shuangchen Li, Xiao Sheng, Daming Zhang, Mei-Fang Chiang, Baiko Sai, Xiaobo Sharon Hu, Huazhong Yang
PaCC: A Parallel Compare and Compress Codec for Area Reduction in Nonvolatile Processors. IEEE Trans. Very Large Scale Integr. Syst. 22 (7) (2014)
Yiqun Wang, Yongpan Liu, Yumeng Liu, Daming Zhang, Shuangchen Li, Baiko Sai, Mei-Fang Chiang, Huazhong Yang
A compression-based area-efficient recovery architecture for nonvolatile processors. DATE (2012)
Yiqun Wang, Yongpan Liu, Shuangchen Li, Daming Zhang, Bo Zhao, Mei-Fang Chiang, Yanxin Yan, Baiko Sai, Huazhong Yang
A 3us wake-up time nonvolatile processor based on ferroelectric flip-flops. ESSCIRC (2012)
Song Chen, Jianwei Shen, Wei Guo, Mei-Fang Chiang, Takeshi Yoshimura
Redundant via Insertion: Removing Design Rule Conflicts and Balancing via Density. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2010)
Mei-Fang Chiang, Takumi Okamoto, Takeshi Yoshimura
Register placement for high-performance circuits. DATE (2009)
Mei-Fang Chiang, Takumi Okamoto, Takeshi Yoshimura
Lagrangian relaxation based register placement for high-performance circuits. ISQED (2009)
Song Chen, Liangwei Ge, Mei-Fang Chiang, Takeshi Yoshimura
Lagrangian Relaxation Based Inter-Layer Signal Via Assignment for 3-D ICs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2009)
Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang, Lumdo Chen, Brian Han
Full-Chip Routing Considering Double-Via Insertion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (5) (2008)
Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang, Lumdo Chen, Brian Han
Novel full-chip gridless routing considering double-via insertion. DAC (2006)