Masahisa Tamura

Publication Activity (10 Years)

Years Active: 1999-2020
Publications (10 Years): 2

Top Topics

Frequency Response

Distributed Object

Top Venues

IEEE J. Solid State Circuits

Publications

Masahisa Tamura, Hideyuki Takano, Hironori Nakahara, Hiroaki Fujita, Naoya Arisaka, Satoru Shinke, Norihito Suzuki, Yutaka Nakada, Yusuke Shinohe, Shinichirou Etou, Tetsuya Fujiwara, Fumitaka Kondo, Ken Yamamoto, Tomohiro Matsumoto, Yasushi Katayama
A 0.5-V BLE Transceiver With a 1.9-mW RX Achieving -96.4-dBm Sensitivity and -27-dBm Tolerance for Intermodulation From Interferers at 6- and 12-MHz Offsets. IEEE J. Solid State Circuits 55 (12) (2020)
Masahisa Tamura, Hideyuki Takano, Satoru Shinke, Hiroaki Fujita, Hironori Nakahara, Norihito Suzuki, Yutaka Nakada, Yusuke Shinohe, Shinichirou Etou, Tetsuya Fujiwara, Yasushi Katayama
30.5 A 0.5V BLE Transceiver with a 1.9mW RX Achieving -96.4dBm Sensitivity and 4.1dB Adjacent Channel Rejection at 1MHz Offset in 22nm FDSOI. ISSCC (2020)
Masahisa Tamura, Ken Iizawa, Munenori Maeda, Jun Kato, Tatsuo Kumano, Yuji Nomura, Toshihiro Ozawa
Distributed object storage toward storage and usage of packet data in a high-speed network. APNOMS (2014)
Masahisa Tamura, Fumitaka Kondo, Katsumi Watanabe, Yasunori Aoki, Yusuke Shinohe, Koki Uchino, Yuhei Hashimoto, Fumihiro Nishiyama, Hiroaki Miyachi, Ikuho Nagase, Itaru Uezono, Rie Hisamura, Itaru Maekawa
A 1V 357Mb/s-throughput transferjet™ SoC with embedded transceiver and digital baseband in 90nm CMOS. ISSCC (2012)
Masahisa Tamura, Masaru Kitsuregawa
Dynamic Load Balancing for Parallel Association Rule Mining on Heterogenous PC Cluster Systems. VLDB (1999)