Marcin Rogawski

Publication Activity (10 Years)

Years Active: 2003-2016
Publications (10 Years): 1

Top Topics

Hardware Architecture

High Speed Networks

Comprehensive Evaluation

Security Breaches

Top Venues

IACR Cryptol. ePrint Arch.

Microprocess. Microsystems

Publications

Malik Umar Sharif, Rabia Shahid, Kris Gaj, Marcin Rogawski
Hardware-software codesign of RSA for optimal performance vs. flexibility trade-off. FPL (2016)
Pawel Morawiecki, Kris Gaj, Ekawat Homsirikamol, Krystian Matusiewicz, Josef Pieprzyk, Marcin Rogawski, Marian Srebrny, Marcin Wójcik
ICEPOLE: High-Speed, Hardware-Oriented Authenticated Encryption. CHES (2014)
Pawel Morawiecki, Kris Gaj, Ekawat Homsirikamol, Krystian Matusiewicz, Josef Pieprzyk, Marcin Rogawski, Marian Srebrny, Marcin Wójcik
ICEPOLE: High-speed, Hardware-oriented Authenticated Encryption. IACR Cryptol. ePrint Arch. 2014 (2014)
Marcin Rogawski, Ekawat Homsirikamol, Kris Gaj
A novel modular adder for one thousand bits and more using fast carry chains of modern FPGAs. FPL (2014)
Marcin Rogawski, Kris Gaj, Ekawat Homsirikamol
A high-speed unified hardware architecture for 128 and 256-bit security levels of AES and the SHA-3 candidate Grøstl. Microprocess. Microsystems 37 (6-7) (2013)
Marcin Rogawski, Kris Gaj
A High-Speed Unified Hardware Architecture for AES and the SHA-3 Candidate Grøstl. DSD (2012)
Kris Gaj, Ekawat Homsirikamol, Marcin Rogawski, Rabia Shahid, Malik Umar Sharif
Comprehensive Evaluation of High-Speed and Medium-Speed Implementations of Five SHA-3 Finalists Using Xilinx and Altera FPGAs. IACR Cryptol. ePrint Arch. 2012 (2012)
Ekawat Homsirikamol, Pawel Morawiecki, Marcin Rogawski, Marian Srebrny
Security Margin Evaluation of SHA-3 Contest Finalists through SAT-Based Attacks. CISIM (2012)
Ekawat Homsirikamol, Pawel Morawiecki, Marcin Rogawski, Marian Srebrny
Security margin evaluation of SHA-3 contest finalists through SAT-based attacks. IACR Cryptol. ePrint Arch. 2012 (2012)
Rabia Shahid, Malik Umar Sharif, Marcin Rogawski, Kris Gaj
Use of embedded FPGA resources in implementations of 14 round 2 SHA-3 candidates. FPT (2011)
Ekawat Homsirikamol, Marcin Rogawski, Kris Gaj
Throughput vs. Area Trade-offs in High-Speed Architectures of Five Round 3 SHA-3 Candidates Implemented Using Xilinx and Altera FPGAs. CHES (2011)
Marcin Rogawski, Kris Gaj
Groestl Tweaks and their Effect on FPGA Results. IACR Cryptol. ePrint Arch. 2011 (2011)
Ahmad Salman, Marcin Rogawski, Jens-Peter Kaps
Efficient Hardware Accelerator for IPSec Based on Partial Reconfiguration on Xilinx FPGAs. ReConFig (2011)
Kris Gaj, Soonhak Kwon, Patrick Baier, Paul Kohlbrenner, Hoang Le, Mohammed Khaleeluddin, Ramakrishna Bachimanchi, Marcin Rogawski
Area-Time Efficient Implementation of the Elliptic Curve Method of Factoring in Reconfigurable Hardware for Application in the Number Field Sieve. IEEE Trans. Computers 59 (9) (2010)
Kris Gaj, Ekawat Homsirikamol, Marcin Rogawski
Fair and Comprehensive Methodology for Comparing Hardware Performance of Fourteen Round Two SHA-3 Candidates Using FPGAs. CHES (2010)
Ekawat Homsirikamol, Marcin Rogawski, Kris Gaj
Comparing Hardware Performance of Fourteen Round Two SHA-3 Candidates Using FPGAs. IACR Cryptol. ePrint Arch. 2010 (2010)
Kris Gaj, Jens-Peter Kaps, Venkata Amirineni, Marcin Rogawski, Ekawat Homsirikamol, Benjamin Y. Brewster
ATHENa - Automated Tool for Hardware EvaluatioN: Toward Fair and Comprehensive Benchmarking of Cryptographic Hardware Using FPGAs. FPL (2010)
Marcin Rogawski
Analysis of Implementation Hierocrypt-3 algorithm (and its comparison to Camellia algorithm) using ALTERA devices. IACR Cryptol. ePrint Arch. 2003 (2003)
Marcin Rogawski
Analysis of Implementation Hierocrypt-3 algorithm (and its comparison to Camellia algorithm) using ALTERA devices CoRR (2003)