Throughput vs. Area Trade-offs in High-Speed Architectures of Five Round 3 SHA-3 Candidates Implemented Using Xilinx and Altera FPGAs.
Ekawat HomsirikamolMarcin RogawskiKris GajPublished in: CHES (2011)
Keyphrases
- high speed
- field programmable gate array
- hardware implementation
- trade off
- fpga device
- pipelined architecture
- hardware design
- low latency
- embedded systems
- low power
- parallel computing
- fpga implementation
- real time
- programmable logic
- reconfigurable hardware
- response time
- parallel architectures
- image processing algorithms
- computing systems
- high speed networks
- software implementation
- frame rate
- image sequences