A High-Speed Unified Hardware Architecture for AES and the SHA-3 Candidate Grøstl.

Marcin Rogawski Kris Gaj

Published in: DSD (2012)

Keyphrases

hardware architecture
high speed
hardware implementation
low power
hardware architectures
field programmable gate array
associative memory
real time
numerically stable
hash functions
secret key
pairwise
processing elements
encryption algorithm
image processing
xilinx virtex
neural network