A high-speed unified hardware architecture for 128 and 256-bit security levels of AES and the SHA-3 candidate Grøstl.
Marcin RogawskiKris GajEkawat HomsirikamolPublished in: Microprocess. Microsystems (2013)
Keyphrases
- hardware architecture
- high speed
- advanced encryption standard
- block cipher
- hash functions
- encryption algorithms
- hardware implementation
- s box
- hardware architectures
- cryptographic algorithms
- encryption algorithm
- xilinx virtex
- encryption decryption
- low power
- secret key
- security requirements
- associative memory
- information security
- access control
- fault model
- random number generator
- security protocols
- real time
- block matching motion estimation
- processing elements
- pseudorandom
- field programmable gate array
- neural network
- key management
- smart card
- pattern recognition