Khosrov Dabbagh-Sadeghipour

Publication Activity (10 Years)

Years Active: 2003-2022
Publications (10 Years): 1

Top Topics

Piecewise Constant

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Meysam M. Khanghah, Khosrov Dabbagh-Sadeghipour, Denis Kelly, Cleitus Antony, Peter Ossieur, Paul D. Townsend
A 7-Bit 7-GHz Multiphase Interpolator-Based DPC for CDR Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (10) (2022)
Khosrov Dabbagh-Sadeghipour, Paul D. Townsend, Peter Ossieur
Design of a sample-and-hold analog front end for a 56Gb/s PAM-4 receiver using 65nm CMOS. ISCAS (2015)
Khosrov Dabbagh-Sadeghipour
An accurate track-and-latch comparator. IEICE Electron. Express 9 (8) (2012)
Khosrov Dabbagh-Sadeghipour, Asgar Abbaszadeh
Efficient realization of reconfigurable FIR filter using the new coefficient representation. IEICE Electron. Express 8 (12) (2011)
Asgar Abbaszadeh, Anasystem Azerbaijan, Khosrov Dabbagh-Sadeghipour
A new hardware efficient reconfigurable fir filter architecture suitable for FPGA applications. DSP (2011)
Khosrov Dabbagh-Sadeghipour
A new offset cancelled latch comparator for high-speed, low-power ADCs. APCCAS (2010)
Asgar Abbaszadeh, Khosrov Dabbagh-Sadeghipour
A new FPGA-based postprocessor architecture for channel mismatch correction of time interleaved ADCS. SiPS (2009)
Khosrov Dabbagh-Sadeghipour
A new wideband, high-linear passive Sample and Hold structure suitable for high-speed, high-resolution ADCs. APCCAS (2008)
Khosrov Dabbagh-Sadeghipour, Ali Aghagolzadeh
A new hardware efficient, low power FIR digital filter implementation approach. ICECS (2003)