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Design of a sample-and-hold analog front end for a 56Gb/s PAM-4 receiver using 65nm CMOS.
Khosrov Dabbagh-Sadeghipour
Paul D. Townsend
Peter Ossieur
Published in:
ISCAS (2015)
Keyphrases
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circuit design
high speed
design process
analog vlsi
case study
low cost
software architecture
cmos image sensor
digital computer
single chip
analog to digital converter
data sets
vlsi architecture
image sensor
back end
engineering design
low power
computer aided
sample size