Kenichi Kawasaki

Publication Activity (10 Years)

Years Active: 2006-2013
Publications (10 Years): 0

Top Topics

Power Reduction

Brain Image Registration

Single Modality

Top Venues

Publications

Kentaro Kawakami, Takeshi Shiro, Hironobu Yamasaki, Katsuhiro Yoda, Hiroaki Fujimoto, Kenichi Kawasaki, Yasuhiro Watanabe
Peak power reduction of a sensor network processor fabricated with Deeply Depleted Channel transistors in 65nm technology. ISQED (2013)
Yusuke Tanaka, Yasufumi Hino, Yasuhiro Okada, Takahiro Takeda, Sho Ohashi, Hiroyuki Yamagishi, Kenichi Kawasaki, Ali Hajimiri
A versatile multi-modality serial link. ISSCC (2012)
Satoshi Fukuda, Yasufumi Hino, Sho Ohashi, Takahiro Takeda, Hiroyuki Yamagishi, Satoru Shinke, Kenji Komori, Masahiro Uno, Yoshiyuki Akiyama, Kenichi Kawasaki, Ali Hajimiri
A 12.5+12.5 Gb/s Full-Duplex Plastic Waveguide Interconnect. IEEE J. Solid State Circuits 46 (12) (2011)
Satoshi Fukuda, Yasufumi Hino, Sho Ohashi, Takahiro Takeda, Satoru Shinke, Masahiro Uno, Kenji Komori, Yoshiyuki Akiyama, Kenichi Kawasaki, Ali Hajimiri
A 12.5+12.5Gb/s full-duplex plastic waveguide interconnect. ISSCC (2011)
Kenichi Kawasaki, Yoshiyuki Akiyama, Kenji Komori, Masahiro Uno, Hidenori Takeuchi, Tomoari Itagaki, Yasufumi Hino, Yoshinobu Kawasaki, Katsuhisa Ito, Ali Hajimiri
A millimeter-wave intra-connect solution. ISSCC (2010)
Kenichi Kawasaki, Yoshiyuki Akiyama, Kenji Komori, Masahiro Uno, Hidenori Takeuchi, Tomoari Itagaki, Yasufumi Hino, Yoshinobu Kawasaki, Katsuhisa Ito, Ali Hajimiri
A Millimeter-Wave Intra-Connect Solution. IEEE J. Solid State Circuits 45 (12) (2010)
Kenichi Kawasaki, Tetsuyoshi Shiota, Koichi Nakayama, Atsuki Inoue
A Sub-µs Wake-Up Time Power Gating Technique With Bypass Power Line for Rush Current Support. IEEE J. Solid State Circuits 44 (4) (2009)
Satoshi Imai, Atsuki Inoue, Motoaki Matsumura, Kenichi Kawasaki, Atsuhiro Suga
Single-chip multi-processor integrating quadruple 8-way VLIW processors with interface timing analysis considering power supply noise. ASP-DAC (2006)