Peak power reduction of a sensor network processor fabricated with Deeply Depleted Channel transistors in 65nm technology.
Kentaro KawakamiTakeshi ShiroHironobu YamasakiKatsuhiro YodaHiroaki FujimotoKenichi KawasakiYasuhiro WatanabePublished in: ISQED (2013)
Keyphrases
- power reduction
- sensor networks
- nm technology
- low power
- high speed
- cmos technology
- power consumption
- power dissipation
- energy efficiency
- wireless sensor networks
- power saving
- sensor data
- multi channel
- low cost
- energy efficient
- sensor nodes
- data streams
- energy consumption
- digital signal processing
- base station
- energy saving
- real time
- design methodology
- routing protocol
- computer vision
- wireless channels