Junichi Hirase

Publication Activity (10 Years)

Years Active: 1995-2014
Publications (10 Years): 0

Top Topics

Multi Dimensional

Manufacturing Processes

Top Venues

IEICE Trans. Electron.

Publications

Junichi Hirase
Introduction of Yield Quadrant and Yield Capability Index for VLSI Manufacturing. IEICE Trans. Electron. (6) (2014)
Junichi Hirase
Verification of Moore's Law Using Actual Semiconductor Production Data. IEICE Trans. Electron. (6) (2014)
Junichi Hirase
Defect Detection Rate through IDDQ for Production Testing. ATS (2008)
Junichi Hirase, Yoshiyuki Goi, Yoshiyuki Tanaka
IDDQ Testing Method using a Scan Pattern for Production Testing. Asian Test Symposium (2005)
Junichi Hirase, Tatsuya Furukawa
Chip Identification using the Characteristic Dispersion of Transistor. Asian Test Symposium (2005)
Junichi Hirase
Test Pattern Length Required to Reach the Desired Fault Coverage. Asian Test Symposium (2003)
Junichi Hirase
High Precision Result Evaluation of VLSI. Asian Test Symposium (2002)
Junichi Hirase
Test Time Reduction through Minimum Execution of Tester-Hardware Setting Instructions. Asian Test Symposium (2001)
Junichi Hirase
Yield Increase of VLSI after Redundancy-Repairing. Asian Test Symposium (2001)
Junichi Hirase, Shinichi Yoshimura
Faster processing for microprocessor functional ATPG. Asian Test Symposium (2000)
Junichi Hirase, Shinichi Yoshimura, Tomohisa Sczaki
Automatic Test Pattern Generation for Improving the Fault Coverage of Microprocessors. Asian Test Symposium (1999)
Junichi Hirase, Naoki Shindou, Kouji Akahori
Scan Chain Diagnosis Using IDDQ Current Measurement. Asian Test Symposium (1999)
Junichi Hirase
Economical Importance of the Maximum Chip Area. Asian Test Symposium (1998)
Junichi Hirase
Improvement of the Defect Level of Micro-computer LSI Testing. ITC (1995)
Junichi Hirase
Study on the Costs of On-site VLSI Testing. ITC (1995)
Junichi Hirase, Masanori Hamada
The Effect of CMOS VLSI IDDq Measurement on Defect Level. IEICE Trans. Inf. Syst. (7) (1995)