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Jian Wu
ORCID
Publication Activity (10 Years)
Years Active: 2011-2016
Publications (10 Years): 1
Top Topics
Cmos Technology
Error Resilience
High Voltage
Power Dissipation
Top Venues
Microelectron. Reliab.
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Publications
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Shuai Zhang
,
Hsiao-Chin Tuan
,
Xiaojing Wu
,
Lei Shi
,
Jian Wu
300-V class power n-channel LDMOS transistor implemented in 0.18-μm silicon-on-insulator (SOI) technology.
Microelectron. Reliab.
61 (2016)
Fei Ma
,
Yan Han
,
Shurong Dong
,
Meng Miao
,
Jianfeng Zheng
,
Jian Wu
,
Cheng-gong Han
,
Kehan Zhu
Investigation of ESD protection strategy in high voltage Bipolar-CMOS-DMOS process.
Microelectron. Reliab.
52 (8) (2012)
Jian Wu
,
Shurong Dong
,
Mingliang Li
,
Meng Miao
,
Fei Ma
,
Jianfeng Zheng
,
Yan Han
A novel power-clamp assisted complementary MOSFET for robust ESD protection.
Microelectron. Reliab.
52 (8) (2012)
Meng Miao
,
Shurong Dong
,
Mingliang Li
,
Jian Wu
,
Fei Ma
,
Jianfeng Zheng
,
Yan Han
A novel gate-suppression technique for ESD protection.
Microelectron. Reliab.
52 (8) (2012)
Fei Ma
,
Yan Han
,
Bo Song
,
Shurong Dong
,
Meng Miao
,
Jianfeng Zheng
,
Jian Wu
,
Kehan Zhu
Substrate-engineered GGNMOS for low trigger voltage ESD in 65 nm CMOS process.
Microelectron. Reliab.
51 (12) (2011)