Jeff Sondeen

Publication Activity (10 Years)

Years Active: 2002-2009
Publications (10 Years): 0

Publications

Young Hoon Kang, Jeff Sondeen, Jeffrey T. Draper
Multicast routing with dynamic packet fragmentation. ACM Great Lakes Symposium on VLSI (2009)
Taek-Jun Kwon, Jeff Sondeen, Jeff Draper
Floating-point division and square root implementation using a Taylor-series expansion algorithm. ICECS (2008)
Tim Barrett, Sumit D. Mediratta, Taek-Jun Kwon, Ravinder Singh, Sachit Chandra, Jeff Sondeen, Jeffrey T. Draper
A double-data rate (DDR) processing-in-memory (PIM) device with wideword floating-point capability. ISCAS (2006)
Sumit D. Mediratta, Craig S. Steele, Jeff Sondeen, Jeffrey T. Draper
An area-efficient and protected network interface for processing-in-memory systems. ISCAS (3) (2005)
Jeffrey T. Draper, Tim Barrett, Jeff Sondeen, Sumit D. Mediratta, Chang Woo Kang, Ihn Kim, Gokhan Daglikoca
A Prototype Processing-In-Memory (PIM) Chip for the Data-Intensive Architecture (DIVA) System. J. VLSI Signal Process. 40 (1) (2005)
Taek-Jun Kwon, Jeff Sondeen, Jeffrey T. Draper
Design trade-offs in floating-point unit implementation for embedded and processing-in-memory systems. ISCAS (4) (2005)
Taek-Jun Kwon, Joong-Seok Moon, Jeff Sondeen, Jeffrey T. Draper
A 0.18 µm implementation of a floating-point unit for a processing-in-memory system. ISCAS (2) (2004)
Sumit D. Mediratta, Jeff Sondeen, Jeffrey T. Draper
An Area-Efficient Router for the Data-Intensive Architecture (DIVA) System. VLSI Design (2004)
Joong-Seok Moon, Taek-Jun Kwon, Jeff Sondeen, Jeffrey Draper
An area-efficient standard-cell floating-point unit design for a processing-in-memory system. ESSCIRC (2003)
Jeffrey T. Draper, Jeff Sondeen, Sumit D. Mediratta, Ihn Kim
Implementation of a 32-bit RISC Processor for the Data-Intensive Architecture Processing-In-Memory Chip. ASAP (2002)