Jeff L. Sonntag

Publication Activity (10 Years)

Years Active: 2000-2006
Publications (10 Years): 0

Publications

Jeff L. Sonntag, John T. Stonick
A Digital Clock and Data Recovery Architecture for Multi-Gigabit/s Binary Links. IEEE J. Solid State Circuits 41 (8) (2006)
David A. Yokoyama-Martin, Kannan Krishna, John T. Stonick, Aaron Caffee, E. K. Gamble, Chris Jones, J. Mcneal, James Parker, Ross Segelken, Jeff L. Sonntag, K. Umino, J. Upton, Daniel Weinlader, Skye Wolfer
A Multi-Standard Low Power 1.5-3.125 Gb/s Serial Transceiver in 90nm CMOS. CICC (2006)
Kannan Krishna, David A. Yokoyama-Martin, Aaron Caffee, Chris Jones, Mat Loikkanen, James Parker, Ross Segelken, Jeff L. Sonntag, John T. Stonick, Steve Titus, Daniel Weinlader, Skye Wolfer
A multigigabit backplane transceiver core in 0.13-/spl mu/m CMOS with a power-efficient equalization architecture. IEEE J. Solid State Circuits 40 (12) (2005)
Jeff L. Sonntag, John T. Stonick
A digital clock and data recovery architecture for multi-gigabit/s binary links. CICC (2005)
John T. Stonick, Gu-Yeon Wei, Jeff L. Sonntag, Daniel Weinlader
An adaptive PAM-4 5-Gb/s backplane transceiver in 0.25-μm CMOS. IEEE J. Solid State Circuits 38 (3) (2003)
Inkyu Lee, Jeff L. Sonntag
A new architecture for the fast Viterbi algorithm. IEEE Trans. Commun. 51 (10) (2003)
Jeff L. Sonntag, John T. Stonick, James Gorecki, Bill Beale, Bill Check, Xue-Mei Gong, Joe Guiliano, Kyong Lee, Bob Lefferts, David A. Yokoyama-Martin, Un-Ku Moon, Amber Sengir, Stephen Titus, Gu-Yeon Wei, Daniel Weinlader, YaoHua Yang
An adaptive PAM-4 5 Gb/s backplane transceiver in 0.25 μm CMOS. CICC (2002)
Inkyu Lee, Jeff L. Sonntag
A new architecture for the fast Viterbi algorithm. GLOBECOM (2000)