A multigigabit backplane transceiver core in 0.13-/spl mu/m CMOS with a power-efficient equalization architecture.
Kannan KrishnaDavid A. Yokoyama-MartinAaron CaffeeChris JonesMat LoikkanenJames ParkerRoss SegelkenJeff L. SonntagJohn T. StonickSteve TitusDaniel WeinladerSkye WolferPublished in: IEEE J. Solid State Circuits (2005)