A Multi-Standard Low Power 1.5-3.125 Gb/s Serial Transceiver in 90nm CMOS.
David A. Yokoyama-MartinKannan KrishnaJohn T. StonickAaron CaffeeE. K. GambleChris JonesJ. McnealJames ParkerRoss SegelkenJeff L. SonntagK. UminoJ. UptonDaniel WeinladerSkye WolferPublished in: CICC (2006)
Keyphrases
- low power
- high speed
- cmos technology
- ultra low power
- power consumption
- low cost
- wireless transmission
- nm technology
- single chip
- power reduction
- vlsi circuits
- high power
- digital signal processing
- vlsi architecture
- low power consumption
- power dissipation
- power saving
- logic circuits
- low voltage
- mixed signal
- delay insensitive
- real time