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An adaptive PAM-4 5-Gb/s backplane transceiver in 0.25-μm CMOS.

John T. StonickGu-Yeon WeiJeff L. SonntagDaniel Weinlader
Published in: IEEE J. Solid State Circuits (2003)
Keyphrases
  • high speed
  • ultra low power
  • power consumption
  • low power
  • circuit design
  • delay insensitive
  • low cost
  • vlsi circuits
  • database
  • frequency response
  • analog vlsi
  • operating system
  • adaptive learning
  • single chip
  • ultra wideband