Jay J. Nejedlo

Publication Activity (10 Years)

Years Active: 2003-2011
Publications (10 Years): 0

Publications

Changhui Hu, Rahul Khanna, Jay J. Nejedlo, Kangmin Hu, Huaping Liu, Patrick Yin Chiang
A 90 nm-CMOS, 500 Mbps, 3-5 GHz Fully-Integrated IR-UWB Transceiver With Multipath Equalization Using Pulse Injection-Locking for Receiver Phase Synchronization. IEEE J. Solid State Circuits 46 (5) (2011)
Patrick Yin Chiang, Sirikarn Woracheewan, Changhui Hu, Lei Guo, Rahul Khanna, Jay J. Nejedlo, Huaping Liu
Short-Range, Wireless Interconnect within a Computing Chassis: Design Challenges. IEEE Des. Test Comput. 27 (4) (2010)
Jay J. Nejedlo, Rahul Khanna
IBIST, the full vision realized. ITC (2009)
Jay J. Nejedlo
Functional Test Coverage Effectiveness on the Decline. ITC (2004)
Jay J. Nejedlo
IBISTTM (Interconnect Built-in Self-Test) Architecture and Methodology for PCI Express: Intel?s Next-Generation Test and Validation Methodology for Performance IO. ITC (2003)
Jay J. Nejedlo
TRIBuTETM Board and Platform Test Methodology: Intel's Next-Generation Test and Validation Methodology for Platforms. ITC (2003)