James Coole

Publication Activity (10 Years)

Years Active: 2008-2018
Publications (10 Years): 3

Top Topics

Field Programmable Gate Array

Hardware Architectures

Top Venues

Publications

David Wilson, Greg Stitt, James Coole
A Recurrently Generated Overlay Architecture for Rapid FPGA Application Development. HEART (2018)
Anshuman Verma, Huiyang Zhou, Skip Booth, Robbie King, James Coole, Andy Keep, John Marshall, Wu-chun Feng
Developing Dynamic Profiling and Debugging Support in OpenCL for FPGAs. DAC (2017)
James Coole, Greg Stitt
Adjustable-Cost Overlays for Runtime Compilation. FCCM (2015)
James Coole, Greg Stitt
Fast, Flexible High-Level Synthesis from OpenCL using Reconfiguration Contexts. IEEE Micro 34 (1) (2014)
James Coole, Greg Stitt
BPR: fast FPGA placement and routing using macroblocks. CODES+ISSS (2012)
Greg Stitt, Alan D. George, Herman Lam, Melissa C. Smith, Vikas Aggarwal, Gongyu Wang, Casey Reardon, Brian Holland, Seth Koehler, James Coole
An End-to-End Tool Flow for FPGA-Accelerated Scientific Computing. IEEE Des. Test Comput. 28 (4) (2011)
Greg Stitt, James Coole
Intermediate Fabrics: Virtual Architectures for Near-Instant FPGA Compilation. IEEE Embed. Syst. Lett. 3 (3) (2011)
James Coole, Greg Stitt
Intermediate fabrics: virtual architectures for circuit portability and fast placement and routing. CODES+ISSS (2010)
James Coole, Greg Stitt
Traversal Caches: A Framework for FPGA Acceleration of Pointer Data Structures. Int. J. Reconfigurable Comput. 2010 (2010)
James Coole, John Robert Wernsing, Greg Stitt
A Traversal Cache Framework for FPGA Acceleration of Pointer Data Structures: A Case Study on Barnes-Hut N-body Simulation. ReConFig (2009)
Greg Stitt, Gaurav Chaudhari, James Coole
Traversal caches: a first step towards FPGA acceleration of pointer-based data structures. CODES+ISSS (2008)