BPR: fast FPGA placement and routing using macroblocks.
James CooleGreg StittPublished in: CODES+ISSS (2012)
Keyphrases
- error propagation
- error concealment
- bit rate
- rate distortion
- real time image processing
- field programmable gate array
- high speed
- routing problem
- hardware implementation
- network topology
- ad hoc networks
- routing protocol
- routing algorithm
- motion vectors
- macroblock
- hardware architecture
- real time
- bitstream
- shortest path
- signal processing
- low cost
- verilog hdl
- hardware design
- variable block size
- compressed video
- mobile ad hoc networks
- business processes
- video codec
- single chip
- rate control
- base layer
- motion estimation
- computational complexity