Jacques Benkoski

Publication Activity (10 Years)

Years Active: 1987-2007
Publications (10 Years): 0

Publications

Jacques Benkoski, Michelle Clancy, Shankar Krishnamoorthy, David Holt, Ravi Subramanian, Clive Bittlestone, Tsuyoshi Yamamoto, Andrew Kanhg
Do Digital Design and Variability Mix like Oil and Water? ISQED (2007)
K. Brock, C. Edwards, R. Lannoo, Ulf Schlichtmann, Antun Domic, Jacques Benkoski, David Overhauser, M. Kliment
Power Crisis in SoC Design: Strategies for Constructing Low-Power, High-Performance SoC Designs. DATE (2002)
Bill Alexander, Jacques Benkoski
0.13 micron: Will the Speed Bumps Slow the Race to Market? ISQED (2001)
Robert N. Blair, Jacques Benkoski
How Do You Select A High Quality EDA Tool Flow?. ISQED (2000)
Gilles Fourneris, Nourouddine Bekkara, Jacques Benkoski, Lucia Zullino, Dino Spatafora, Giuseppe Martino
Demosthenes-A technology-independent power DMOS layout generator. EURO-DAC (1993)
Ronald B. Stewart, Véronique Anjubault, Philippe Garcin, Jacques Benkoski
Automatic import of custom designs into a cell-based environment using switch-level analysis and circuit simulation. EURO-DAC (1992)
Joel Besnard, Jacques Benkoski, Bernard Hennion
Eldo-XL: a software accelerator for the analysis of digital MOS circuits by an analog simulator. EURO-DAC (1991)
Jacques Benkoski, Andrzej J. Strojwas
The Role of Timing Verification in Layout Synthesis. DAC (1991)
Ronald B. Stewart, Jacques Benkoski
Static Timing Analysis Using Interval Constraints. ICCAD (1991)
Jacques Benkoski, Ronald B. Stewart
TATOO: an industrial timing analyzer with false path elimination and test pattern generation. EURO-DAC (1991)
Jacques Benkoski, E. Vanden Meersch, Luc J. M. Claesen, Hugo De Man
Timing verification using statically sensitizable paths. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9 (10) (1990)
Jacques Benkoski, Andrzej J. Strojwas
Computation of Delay Defect and Delay Fault Probabilities Using a Statistical Timing Simulator. ITC (1989)
Jacques Benkoski, Andrzej J. Strojwas
Timing Verification by Formal Signal Interaction Modeling in a Multi-level Timing Simulator. DAC (1989)
Jacques Benkoski, Andrzej J. Strojwas
A New Approach to Hierarchical and Statistical Timing Simulations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6 (6) (1987)