Jack S. N. Jean

Publication Activity (10 Years)

Years Active: 1990-2012
Publications (10 Years): 0

Top Topics

Dynamic Reconfiguration

Operating System

Interprocess Communication

Top Venues

J. Supercomput.

Publications

Fei Wang, Jack S. N. Jean
Architecture and operating system support for two-dimensional runtime partial reconfiguration. J. Supercomput. 59 (2) (2012)
Srikanth Nadella, Andrew Dittes, Jack S. N. Jean
Parameterized AND-OR Trees for FPGA Design Space Exploration. ERSA (2010)
Fei Wang, Jack S. N. Jean
Architectural Support for Runtime 2D Partial Reconfiguration. ERSA (2006)
Fei Wang, Jack S. N. Jean, Shuxia Sun
Aspect Ratio Effects on Reconfigurable Computing. ERSA (2005)
Xinzhong Guo, Jack S. N. Jean
Design Enumeration of Mapping 2D FFT onto FPGA Based Reconfigurable Computers. ERSA (2004)
Jack S. N. Jean, Xinzhong Guo, Fei Wang, Lei Song, Ying Zhang
A Study of Mapping Generalized Sliding Window Operations on Reconfigurable Computers. Engineering of Reconfigurable Systems and Algorithms (2003)
Xuejun Liang, Jack S. N. Jean
Mapping of generalized template matching onto reconfigurable computers. IEEE Trans. Very Large Scale Integr. Syst. 11 (3) (2003)
Xuejun Liang, Jack S. N. Jean, Karen A. Tomko
Data Buffering and Allocation in Mapping Generalized Template Matching on Reconfigurable Systems. J. Supercomput. 19 (1) (2001)
Jack S. N. Jean, Xuejun Liang, Brian Drozd, Karen A. Tomko, Yan Wang
Automatic Target Recognition with Dynamic Reconfiguration. J. VLSI Signal Process. 25 (1) (2000)
Xuejun Liang, Jack S. N. Jean
Interface Design for the Mapping of Generalized Template Matching on Reconfigurable Systems. PDPTA (2000)
Jack S. N. Jean, Xuejun Liang, Karen A. Tomko
Data Buffering and Allocation in Mapping Generalized Template Matching on Reconfigurable Systems. PDPTA (1999)
Jack S. N. Jean, Xuejun Liang, Brian Drozd, Karen A. Tomko
Accelerating an IR Automatic Target Recognition Application with FPGAs. FCCM (1999)
Jack S. N. Jean, Karen A. Tomko, Vikram Yavagal, Jignesh Shah, Robert Cook
Dynamic Reconfiguration to Support Concurrent Applications. IEEE Trans. Computers 48 (6) (1999)
Joseph A. Fernando, Jack S. N. Jean
Processor array design with FPGA area constraint. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (3) (1999)
Hong K. Kim, Jack S. N. Jean
Concurrency Preserving Partitioning Algorithm for Parallel Logic Simulation. VLSI Design 1999 (3) (1999)
Jack S. N. Jean, Karen A. Tomko, Vikram Yavagal, Robert Cook, Jignesh Shah
Dynamic Reconfiguration to Support Concurrent Applications. FCCM (1998)
Hong K. Kim, Jack S. N. Jean
Parallel Optimistic Logic Simulation with Event Lookahead. ICPP (1998)
Hong K. Kim, Jack S. N. Jean
Concurrency Preserving Rartitioning (CPP) for Parallel Logic Simulation. Workshop on Parallel and Distributed Simulation (1996)
Joseph A. Fernando, Jack S. N. Jean
Interfacing FPGA/VLSI Processor Arrays. ASAP (1995)
Jin Wang, Jack S. N. Jean
Segmentation of merged characters by neural networks and shortest path. Pattern Recognit. 27 (5) (1994)
Jack S. N. Jean, Jin Wang
Weight smoothing to improve network generalization. IEEE Trans. Neural Networks 5 (5) (1994)
Jin Wang, Jack S. N. Jean
Segmentation of Merged Characters by Neural Networks and Shortest-Path. SAC (1993)
Jin Wang, Jack S. N. Jean
Resolving multifont character confusion with neural networks. Pattern Recognit. 26 (1) (1993)
Jack S. N. Jean
Fault-tolerant array processors using N-and-half-track switches. ASAP (1990)
Jack S. N. Jean
A new distance measure for binary images. ICASSP (1990)