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Ilya Issenin
Publication Activity (10 Years)
Years Active: 2002-2009
Publications (10 Years): 0
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Publications
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Doosan Cho
,
Sudeep Pasricha
,
Ilya Issenin
,
Nikil D. Dutt
,
Minwook Ahn
,
Yunheung Paek
Adaptive Scratch Pad Memory Management for Dynamic Behavior of Multimedia Applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
28 (4) (2009)
Aviral Shrivastava
,
Ilya Issenin
,
Nikil D. Dutt
,
Sanghyun Park
,
Yunheung Paek
Compiler-in-the-Loop Design Space Exploration Framework for Energy Reduction in Horizontally Partitioned Cache Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
28 (3) (2009)
Kyoungwoo Lee
,
Aviral Shrivastava
,
Ilya Issenin
,
Nikil D. Dutt
,
Nalini Venkatasubramanian
Partially Protected Caches to Reduce Failures Due to Soft Errors in Multimedia Applications.
IEEE Trans. Very Large Scale Integr. Syst.
17 (9) (2009)
Ilya Issenin
,
Erik Brockmeyer
,
Bart Durinck
,
Nikil D. Dutt
Data-Reuse-Driven Energy-Aware Cosynthesis of Scratch Pad Memory and Hierarchical Bus-Based Communication Architecture for Multiprocessor Streaming Applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
27 (8) (2008)
Ilya Issenin
,
Nikil D. Dutt
Using FORAY Models to Enable MPSoC Memory Optimizations.
Int. J. Parallel Program.
36 (1) (2008)
Aviral Shrivastava
,
Ilya Issenin
,
Nikil D. Dutt
A Compiler-in-the-Loop framework to explore Horizontally Partitioned Cache architectures.
ASP-DAC
(2008)
Doosan Cho
,
Sudeep Pasricha
,
Ilya Issenin
,
Nikil D. Dutt
,
Yunheung Paek
,
SunJun Ko
Compiler driven data layout optimization for regular/irregular array access patterns.
LCTES
(2008)
Ilya Issenin
,
Nikil D. Dutt
Data Reuse Driven Memory and Network-On-Chip Co-Synthesis.
IESS
(2007)
Ilya Issenin
,
Erik Brockmeyer
,
Miguel Miranda
,
Nikil D. Dutt
DRDU: A data reuse analysis technique for efficient scratch-pad memory management.
ACM Trans. Design Autom. Electr. Syst.
12 (2) (2007)
Doosan Cho
,
Ilya Issenin
,
Nikil D. Dutt
,
Jonghee W. Yoon
,
Yunheung Paek
Software controlled memory layout reorganization for irregular array access patterns.
CASES
(2007)
Ilya Issenin
,
Nikil D. Dutt
FORAY-GEN: Automatic Generation of Affine Functions for Memory Optimizations
CoRR
(2007)
Ilya Issenin
,
Erik Brockmeyer
,
Bart Durinck
,
Nikil D. Dutt
Multiprocessor system-on-chip data reuse analysis for exploring customized memory hierarchies.
DAC
(2006)
Ilya Issenin
,
Nikil D. Dutt
Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications.
CODES+ISSS
(2006)
Kyoungwoo Lee
,
Aviral Shrivastava
,
Ilya Issenin
,
Nikil D. Dutt
,
Nalini Venkatasubramanian
Mitigating soft error failures for multimedia applications by selective data protection.
CASES
(2006)
Ilya Issenin
,
Nikil D. Dutt
FORAY-GEN: Automatic Generation of Affine Functions for Memory Optimizations.
DATE
(2005)
Aviral Shrivastava
,
Ilya Issenin
,
Nikil D. Dutt
Compilation techniques for energy reduction in horizontally partitioned cache architectures.
CASES
(2005)
Ilya Issenin
,
Erik Brockmeyer
,
Miguel Miranda
,
Nikil D. Dutt
Data Reuse Analysis Technique for Software-Controlled Memory Hierarchies.
DATE
(2004)
Ana Azevedo
,
Ilya Issenin
,
Radu Cornea
,
Rajesh Gupta
,
Nikil D. Dutt
,
Alexander V. Veidenbaum
,
Alexandru Nicolau
Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints.
DATE
(2002)