Horng-Yuan Shih

Publication Activity (10 Years)

Years Active: 2010-2021
Publications (10 Years): 2

Top Topics

Biomedical Images

Wearable Devices

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Horng-Yuan Shih, Chin-Te Hsin, Cheng-Wei Yang, Hsin-Liang Chen, Jhe-Yuan Kuo
A CMOS MEMS Pressure Sensor for Blood Pulse and Pressure Measurement Applications. ISPACS (2021)
Horng-Yuan Shih, Yu-Chuan Chang, Cheng-Wei Yang, Chieh-Chih Chen
A Low-Power and Small Chip-Area Multi-Rate Human Body Communication DPFSK Transceiver for Wearable Devices. IEEE Trans. Circuits Syst. II Express Briefs (7) (2020)
Horng-Yuan Shih, Chun-Fan Chen, Yu-Chuan Chang, Yu-Wei Hu
An Ultralow Power Multirate FSK Demodulator With Digital-Assisted Calibrated Delay-Line Based Phase Shifter for High-Speed Biomedical Zero-IF Receivers. IEEE Trans. Very Large Scale Integr. Syst. 23 (1) (2015)
Horng-Yuan Shih, Sheng-Kai Lin, Po-Shun Liao
An 80× Analog-Implemented Time-Difference Amplifier for Delay-Line-Based Coarse-Fine Time-to-Digital Converters in 0.18-µm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 23 (8) (2015)
Horng-Yuan Shih, Yu-Wei Hu, Cheng-Wei Yang, Yi-Wei Hong
An ultra-low power multi-rate FSK transmitter for wireless sensors and biomedical applications. ICEIC (2014)
Horng-Yuan Shih, Wei-Hsien Chen, Kai-Chenug Juang, Chun-Fan Chen, Sheng-Kai Lin
A ultra-low power channel selection filter for low-IF FSK biomedical receivers. ISPACS (2012)
Horng-Yuan Shih, Chih-Wei Wang
A Highly-Integrated 3-8 GHz Ultra-Wideband RF Transmitter With Digital-Assisted Carrier Leakage Calibration and Automatic Transmit Power Control. IEEE Trans. Very Large Scale Integr. Syst. 20 (8) (2012)
Horng-Yuan Shih, Chien-Nan Kuo, Wei-Hsien Chen, Tzu-Yi Yang, Kai-Chenug Juang
A 250 MHz 14 dB-NF 73 dB-Gain 82 dB-DR Analog Baseband Chain With Digital-Assisted DC-Offset Calibration for Ultra-Wideband. IEEE J. Solid State Circuits 45 (2) (2010)
Chiou-Bang Chen, Horng-Yuan Shih
A 400 MHz 0.934ps rms jitter multiplying delay lock loop in 90-nm CMOS process. ICECS (2010)