A 400 MHz 0.934ps rms jitter multiplying delay lock loop in 90-nm CMOS process.
Chiou-Bang ChenHorng-Yuan ShihPublished in: ICECS (2010)
Keyphrases
- end to end delay
- cmos technology
- power dissipation
- power consumption
- high speed
- nm technology
- low power
- packet loss
- ad hoc networks
- concurrency control
- routing protocol
- infrared
- database
- high frequency
- video transmission
- wireless networks
- logic programs
- critical path
- root mean square
- locking protocol
- transmission electron microscopy