Harsha Sathyamurthy

Publication Activity (10 Years)

Years Active: 1995-1998
Publications (10 Years): 0

Publications

Harsha Sathyamurthy, Sachin S. Sapatnekar, John P. Fishburn
Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17 (2) (1998)
Harsha Sathyamurthy, Sachin S. Sapatnekar, John P. Fishburn
Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization. ICCAD (1995)