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Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization.
Harsha Sathyamurthy
Sachin S. Sapatnekar
John P. Fishburn
Published in:
ICCAD (1995)
Keyphrases
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high speed
optimization algorithm
power consumption
optimization process
cmos technology
power losses
real time
simulated annealing
global optimization
low power
optimization problems
combinatorial optimization
data flow
discrete optimization
multiple input
electronic circuits