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Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization.
Harsha Sathyamurthy
Sachin S. Sapatnekar
John P. Fishburn
Published in:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (1998)
Keyphrases
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high speed
power losses
optimization problems
power consumption
global optimization
optimization methods
cmos technology
optimization algorithm
optimization method
optimization process
discrete optimization
database systems
low cost
data flow
logic synthesis