Hae-Wook Choi

Publication Activity (10 Years)

Years Active: 1995-2014
Publications (10 Years): 0

Top Topics

Geographical Information Systems

Top Venues

Publications

Hae Young Rha, Byoung Gu Jeon, Hae-Wook Choi
Efficient guard interval reduction for coherent optical OFDM. OFC (2014)
Thu Phuong Nguyen, Minh-Tuan Le, Vu-Duc Ngo, Xuan-Nam Tran, Hae-Wook Choi
Spatial Modulation for High-Rate Transmission Systems. VTC Spring (2014)
Hun-sik Kang, Min-Lee Hwang, Jin Lee, Sok-Kyu Lee, Hae-Wook Choi, Sin-Chong Park
A Calibration Scheme for Delay Mismatch Compensation in OFDM-Based Polar Transmitter. IEICE Trans. Commun. (10) (2010)
Seongmin Noh, Daehyun Kim, Vu-Duc Ngo, Hae-Wook Choi
Performance and Complexity Analysis of Credit-Based End-to-End Flow Control in Network-on-Chip. ISPA (2007)
Vu-Duc Ngo, June-Young Chang, Younghwan Bae, Hanjin Cho, Hae-Wook Choi
Latency Optimization for NoC Design of H.264 Decoder Based on Self-similar Traffic Modeling. ISPA (2007)
Huy Nam Nguyen, Vu-Duc Ngo, Younghwan Bae, Hanjin Cho, Hae-Wook Choi
An QoS Aware Mapping of Cores Onto NoC Architectures. ISPA (2007)
Sang-Ho Seo, Hae-Wook Choi, Sin-Chong Park
Low Latency and Memory Efficient Viterbi Decoder Using Modified State-Mapping Method. IEICE Trans. Commun. (4) (2006)
Ho-Seok Choi, Hae-Wook Choi, Sin-Chong Park
Instruction Based Synthesizable Testbench Architecture. IEICE Trans. Electron. (5) (2006)
Vu-Duc Ngo, Huy Nam Nguyen, Younghwan Bae, Hanjin Cho, Hae-Wook Choi
Throughput Aware Mapping for Network on Chip Design of H.264 Decoder. ISPA Workshops (2006)
Jungbo Son, Hae-Wook Choi, Sin-Chong Park
Accelerating Verification with Reusable Testbench. IEICE Trans. Inf. Syst. (2) (2006)
Vu-Duc Ngo, Huy Nam Nguyen, Hae-Wook Choi
The Optimum Network on Chip Architectures for Video Object Plane Decoder Design. ISPA (2006)
Vu-Duc Ngo, Huy Nam Nguyen, Hae-Wook Choi
Analyzing the Performance of Mesh and Fat-Tree Topologies for Network on Chip Design. EUC (2005)
Vu-Duc Ngo, Huy Nam Nguyen, Hae-Wook Choi
Designing On-Chip Network Based on Optimal Latency Criteria. ICESS (2005)
Huy Nam Nguyen, Vu-Duc Ngo, Hae-Wook Choi
Realization of Video Object Plane Decoder on On-Chip Network Architecture. ICESS (2005)
Huy Nam Nguyen, Vu-Duc Ngo, Hae-Wook Choi
Realization of video object plane decoder on mesh on-chip network architecture. Circuits, Signals, and Systems (2005)
Vu-Duc Ngo, Hae-Wook Choi, Sin-Chong Park
Expurgated sphere bound for LDPC. PIMRC (2004)
Vu-Duc Ngo, Hae-Wook Choi, Sin-Chong Park
An Expurgated Union Bound for Space-Time Code Systems. ICT (2004)
Won-Chul Song, Hae-Wook Choi, Sung-Ung Kwak, Bang-Sup Song
A 10-b 20-Msample/s low-power CMOS ADC. IEEE J. Solid State Circuits 30 (5) (1995)