H. C. Srinivasaiah

Publication Activity (10 Years)

Years Active: 2002-2017
Publications (10 Years): 1

Top Topics

Delay Insensitive

Spatially Varying

Electrical Properties

Top Venues

J. Circuits Syst. Comput.

Publications

M. C. Parameshwara, H. C. Srinivasaiah
Low-Power Hybrid 1-Bit Full-Adder Circuit for Energy Efficient Arithmetic Applications. J. Circuits Syst. Comput. 26 (1) (2017)
H. C. Srinivasaiah
Implications of Halo Implant Shadowing and Backscattering from Mask Layer Edges on Device Leakage Current in 65nm SRAM. VLSI Design (2012)
H. C. Srinivasaiah, Navakanta Bhat
Response Surface Modeling of 100nm CMOS Process Technology using Design of Experiment. VLSI Design (2004)
H. C. Srinivasaiah, Navakanta Bhat
Mixed-mode simulation approach to characterize the circuit delay sensitivity to implant dose variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22 (6) (2003)
H. C. Srinivasaiah, Navakanta Bhat
Implant Dose Sensitivity of 0.1µm CMOS Inverter Delay. VLSI Design (2002)