Giacomino Bollati

Publication Activity (10 Years)

Years Active: 1997-2020
Publications (10 Years): 2

Top Topics

Power Consumption

Top Venues

IEEE J. Solid State Circuits

Publications

Matteo Pisati, Alberto Minuti, Giacomino Bollati, Fabio Giunco, Roberto G. Massolini, Giovanni Cesura, Fernando De Bernardinis, Paolo Pascale, Claudio Nani, Nicola Ghittori, Enrico Pozzati, Marco Sosio, Marco Garampazzi, Antonio Milani
A 243-mW 1.25-56-Gb/s Continuous Range PAM-4 42.5-dB IL ADC/DAC-Based Transceiver in 7-nm FinFET. IEEE J. Solid State Circuits 55 (1) (2020)
Matteo Pisati, Fernando De Bernardinis, Paolo Pascale, Claudio Nani, Marco Sosio, Enrico Pozzati, Nicola Ghittori, Federico Magni, Marco Garampazzi, Giacomino Bollati, Antonio Milani, Alberto Minuti, Fabio Giunco, Paola Uggetti, Ivan Fabiano, Nicola Codega, Alessandro Bosi, Nicola Carta, Demetrio Pellicone, Giorgio Spelgatti, Massimo Cutrupi, Andrea Rossini, Roberto G. Massolini, Giovanni Cesura, Ivan Bietti
A Sub-250mW 1-to-56Gb/s Continuous-Range PAM-4 42.5dB IL ADC/DAC-Based Transceiver in 7nm FinFET. ISSCC (2019)
Andrea Baschirotto, Giacomino Bollati, Vittorio Colonna, Gabriele Gandolfi
A 94dB-SNR -76dB-THD high-efficiency hybrid audio power-DAC for loudspeaker (4Ω/8Ω) and earphone (16Ω/32Ω). ESSCIRC (2010)
Alex Lollio, Giacomino Bollati, Rinaldo Castello
A Class-G Headphone Amplifier in 65 nm CMOS Technology. IEEE J. Solid State Circuits 45 (12) (2010)
Alex Lollio, Giacomino Bollati, Rinaldo Castello
Class-G headphone driver in 65nm CMOS technology. ISSCC (2010)
Giacomino Bollati, Stefano Marchese, Marco Demicheli, Rinaldo Castello
An eighth-order CMOS low-pass filter with 30-120 MHz tuning range and programmable boost. IEEE J. Solid State Circuits 36 (7) (2001)
Giacomino Bollati, Angelo Dati, Giorgio Betti, Ivan Bietti, Francesco Brianti, Melchiorre Bruccoleri, M. Coltella, P. Demartini, Marco Demicheli, Paolo Gadducci, Stefano Marchese, Daniele Ottini, Valerio Pisati, Francesco Rezzi, A. Rossi, P. Savo, C. Tonci, Rinaldo Castello
A 450 Mbit/s parallel read/write channel with parity check and 16-state time variant Viterbi. CICC (2000)
Marco Demicheli, Giacomino Bollati, Paolo Gadducci, L. Affortunati, R. Alini, G. Betti, I. Bietti, F. Brianti, M. Bruccoleri, M. Coltella, P. Demartini, Stefano Marchese, D. Ottini, Valerio Pisati, S. Portaluri, A. Rossi, P. Savo, C. Tonci, R. Castello
A 450 Mbit/s EPR4 PRML read/write channel. CICC (1999)
Roberto Alini, Giorgio Betti, Ivan Bietti, Giacomino Bollati, Francesco Brianti, Angelo Dati, Marco Demicheli, Paolo Gadducci, Stefano Marchese, Emanuele Marconetti, Valerio Pisati, Maurizio Zuffada, Rinaldo Castello, Fereidoon Heydari, Peter Gillen, Gerry Maguire, Marcus Marrow, Stephen McDonagh, Fergus O'Brien, Jerry O'Brien, Niall O'hEarcain, Deirdre Reddy, Lisa Fredrickson, Dennis Stone, LeRoy Volz
A 200-MSample/s trellis-coded PRML read/write channel with analog adaptive equalizer and digital servo. IEEE J. Solid State Circuits 32 (11) (1997)