Ghassem Jaberipur

Publication Activity (10 Years)

Years Active: 2005-2025
Publications (10 Years): 36

Top Topics

Cellular Automata

Top Venues

Comput. Electr. Eng.

IEEE Trans. Very Large Scale Integr. Syst.

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Mohammadreza Najafi, Mohammad K. Fallah, Saeid Gorgin, Ghassem Jaberipur, Jeong-A Lee
Poster: Integration of Wearable and Affective Computing via Abstraction and Decision Fusion Architecture. WoWMoM (2025)
Sahar Moradi Cherati, Ghassem Jaberipur, Leonel Sousa
Sparse Matrix-Vector Multiplication Based on Online Arithmetic. IEEE Access 12 (2024)
Iraj Moghaddasi, Ghassem Jaberipur, Danial Javaheri, Byeong-Gyu Nam
RNPE: An MSDF and Redundant Number System-Based DNN Accelerator Engine. IEEE Access 12 (2024)
Zabihollah Ahmadpour, Ghassem Jaberipur, Jeong-A Lee
Montgomery Modular Multiplication via Single-Base Residue Number Systems. ARITH (2024)
Ghassem Jaberipur, Bardia Nadimi, Jeong-A Lee
+1) Arithmetic via Two Parallel n-bit Residue Channels. CoRR (2024)
Ghassem Jaberipur, Dariush Badri, Jeong-A Lee
+ 1) Adder via Diminished-1 Representation of Residues. IEEE Trans. Circuits Syst. II Express Briefs 70 (8) (2023)
Ghassem Jaberipur, Saeid Gorgin, Navid Ahamadian, Jeong-A Lee
- 3) Multiplication with Fully Modular Partial Product Generation and Reduction. ARITH (2023)
Ghassem Jaberipur, Farzad Ghazanfari
Impact of Radix-10 Redundant Digit Set [-6, 9] on Basic Decimal Arithmetic Operations. IEEE Trans. Very Large Scale Integr. Syst. 30 (1) (2022)
Armin Belghadr, Ghassem Jaberipur
Efficient variable-coefficient RNS-FIR filters with no restriction on the moduli set. Signal Image Video Process. 16 (6) (2022)
Zabihollah Ahmadpour, Ghassem Jaberipur
Up to $8k$8k-bit Modular Montgomery Multiplication in Residue Number Systems With Fast 16-bit Residue Channels. IEEE Trans. Computers 71 (6) (2022)
Adel Hosseiny, Ghassem Jaberipur
Complex exponential functions: A high-precision hardware realization. Integr. 73 (2020)
Ghassem Jaberipur, Bardia Nadimi
Balanced $(3+2\log n)\Delta G$ Adders for Moduli Set $\{{2}^{n+1}, 2^{n}+2^{n-1}-1, 2^{n+1}-1\}$. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. (4) (2020)
Sina Bakhtavari Mamaghani, Mohammad Hossein Moaiyeri, Ghassem Jaberipur
Design of an efficient fully nonvolatile and radiation-hardened majority-based magnetic full adder using FinFET/MTJ. Microelectron. J. 103 (2020)
Behrooz Parhami, Dariush Abedi, Ghassem Jaberipur
Majority-Logic, its applications, and atomic-scale embodiments. Comput. Electr. Eng. 83 (2020)
Zeinab Torabi, Ghassem Jaberipur, Armin Belghadr
-1} based on shortcut mixed radix conversion. Comput. Electr. Eng. 83 (2020)
Ghassem Jaberipur, Sahar Moradi Cherati
Modulo-(2^n+3) Parallel Prefix Addition via Diminished-3 Representation of Residues. ARITH (2019)
Ghassem Jaberipur, Armin Belghadr, Saeed Nejati
Impact of diminished-1 encoding on residue number systems arithmetic units and converters. Comput. Electr. Eng. 75 (2019)
Armin Belghadr, Ghassem Jaberipur
FIR Filter Realization via Deferred End-Around Carry Modular Addition. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2018)
Dariush Abedi, Ghassem Jaberipur
Decimal Full Adders Specially Designed for Quantum-Dot Cellular Automata. IEEE Trans. Circuits Syst. II Express Briefs (1) (2018)
Saba Amanollahi, Ghassem Jaberipur
Extended Redundant-Digit Instruction Set for Energy-Efficient Processors. ACM Trans. Embed. Comput. Syst. 17 (3) (2018)
Ghassem Jaberipur, Behrooz Parhami, Dariush Abedi
Adapting Computer Arithmetic Structures to Sustainable Supercomputing in Low-Power, Majority-Logic Nanotechnologies. IEEE Trans. Sustain. Comput. 3 (4) (2018)
Saba Amanollahi, Ghassem Jaberipur
Fast Energy Efficient Radix-16 Sequential Multiplier. IEEE Embed. Syst. Lett. 9 (3) (2017)
Milad Sangsefidi, Dariush Abedi, Ghassem Jaberipur
Radix-8 full adder in QCA with single clock-zone carry propagation delay. Microprocess. Microsystems 51 (2017)
Ghassem Jaberipur, Armin Belghadr
+1) unified adder/subtractor with full zero handling. Comput. Electr. Eng. 61 (2017)
Saeid Gorgin, Ghassem Jaberipur
Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication. IEEE Trans. Very Large Scale Integr. Syst. 25 (1) (2017)
Saba Amanollahi, Ghassem Jaberipur
Energy-Efficient VLSI Realization of Binary64 Division With Redundant Number Systems. IEEE Trans. Very Large Scale Integr. Syst. 25 (3) (2017)
Morteza Dorrigiv, Ghassem Jaberipur
Conditional speculative mixed decimal/binary adders via binary-coded-chiliad encoding. Comput. Electr. Eng. 50 (2016)
Adel Hosseiny, Ghassem Jaberipur
Decimal Goldschmidt: A hardware algorithm for radix-10 division. Comput. Electr. Eng. 53 (2016)
Zeinab Torabi, Ghassem Jaberipur
-1}. Integr. 55 (2016)
Adel Hosseiny, Ghassem Jaberipur
Decimal Square Root: Algorithm and Hardware Implementation. Circuits Syst. Signal Process. 35 (12) (2016)
Ghassem Jaberipur, Behrooz Parhami, Dariush Abedi
A Formulation of Fast Carry Chains Suitable for Efficient Implementation with Majority Elements. ARITH (2016)
Zeinab Torabi, Ghassem Jaberipur
Low-Power/Cost RNS Comparison via Partitioning the Dynamic Range. IEEE Trans. Very Large Scale Integr. Syst. 24 (5) (2016)
Saeid Gorgin, Ghassem Jaberipur
Comment on "High Speed Parallel Decimal Multiplication With Redundant Internal Encodings". IEEE Trans. Computers 64 (1) (2015)
Seyed Hamed Fatemi Langroudi, Ghassem Jaberipur
- 1) Parallel Prefix Addition via Excess-Modulo Encoding of Residues. ARITH (2015)
HamidReza Ahmadifar, Ghassem Jaberipur
±1}. Comput. J. 58 (7) (2015)
Ghassem Jaberipur, Seyed Hamed Fatemi Langroudi
-3) Adder via Double Representation of Residues in [0, 2]. IEEE Trans. Circuits Syst. II Express Briefs (6) (2015)
Saeid Gorgin, Ghassem Jaberipur, Reza Hashemi Asl
Efficient ASIC and FPGA Implementation of Binary-Coded Decimal Digit Multipliers. Circuits Syst. Signal Process. 33 (12) (2014)
Ghassem Jaberipur, HamidReza Ahmadifar
±3}. IET Comput. Digit. Tech. 8 (1) (2014)
Morteza Dorrigiv, Ghassem Jaberipur
Low area/power decimal addition with carry-select correction and carry-select sum-digits. Integr. 47 (4) (2014)
Seyed Hamed Fatemi Langroudi, Ghassem Jaberipur
- 3) adders. IWSSIP (2014)
Ghassem Jaberipur, Behrooz Parhami
Efficient realisation of arithmetic algorithms with weighted collection of posibits and negabits. IET Comput. Digit. Tech. 6 (5) (2012)
Abdoreza Pishvaie, Ghassem Jaberipur, Ali Jahanian
Improved CMOS (4; 2) compressor designs for parallel multipliers. Comput. Electr. Eng. 38 (6) (2012)
Amir Kaivani, Ghassem Jaberipur
Decimal CORDIC Rotation based on Selection by Rounding: Algorithm and Architecture. Comput. J. 54 (11) (2011)
Ghassem Jaberipur, Behrooz Parhami, Saeed Nejati
On building general modular adders from standard binary arithmetic components. ACSCC (2011)
Amir Kaivani, Adel Hosseiny, Ghassem Jaberipur
Improving the speed of decimal division. IET Comput. Digit. Tech. 5 (5) (2011)
Saeid Gorgin, Ghassem Jaberipur
A Family of High Radix Signed Digit Adders. IEEE Symposium on Computer Arithmetic (2011)
Ghassem Jaberipur, Behrooz Parhami, Saeid Gorgin
Redundant-Digit Floating-Point Addition Scheme Based on a Stored Rounding Value. IEEE Trans. Computers 59 (5) (2010)
Ghassem Jaberipur, Saeid Gorgin
An improved maximally redundant signed digit adder. Comput. Electr. Eng. 36 (3) (2010)
Amir Kaivani, Ghassem Jaberipur
Fully redundant decimal addition and subtraction using stored-unibit encoding. Integr. 43 (1) (2010)
Saeid Gorgin, Ghassem Jaberipur
A fully redundant decimal adder and its application in parallel decimal multipliers. Microelectron. J. 40 (10) (2009)
Ghassem Jaberipur, Behrooz Parhami
+/- 1) Adders Based on Signed-LSB Representation of Residues. IEEE Symposium on Computer Arithmetic (2009)
Saeid Gorgin, Ghassem Jaberipur
Fully Redundant Decimal Arithmetic. IEEE Symposium on Computer Arithmetic (2009)
Ghassem Jaberipur, Amir Kaivani
Improving the Speed of Parallel Decimal Multiplication. IEEE Trans. Computers 58 (11) (2009)
Ghassem Jaberipur, Saeid Gorgin
A Nonspeculative Maximally Redundant Signed Digit Adder. CSICC (2008)
Ghassem Jaberipur, Behrooz Parhami
Constant-time addition with hybrid-redundant numbers: Theory and implementations. Integr. 41 (1) (2008)
Ghassem Jaberipur, Amir Kaivani
Binary-coded decimal digit multipliers. IET Comput. Digit. Tech. 1 (4) (2007)
Ghassem Jaberipur, Behrooz Parhami
Stored-transfer representations with weighted digit-set encodings for ultrahigh-speed arithmetic. IET Circuits Devices Syst. 1 (1) (2007)
Ghassem Jaberipur, Behrooz Parhami, Mohammad Ghodsi
An Efficient Universal Addition Scheme for All Hybrid-Redundant Representations with Weighted Bit-Set Encoding. J. VLSI Signal Process. 42 (2) (2006)
Ghassem Jaberipur, Behrooz Parhami, Mohammad Ghodsi
Weighted two-valued digit-set encodings: unifying efficient hardware representation schemes for redundant number systems. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2005)