Gerald R. Morris

Publication Activity (10 Years)

Years Active: 2005-2013
Publications (10 Years): 0

Top Topics

Floating Point Arithmetic

Heterogeneous Systems

Top Venues

J. Parallel Distributed Comput.

IEEE Trans. Parallel Distributed Syst.

Publications

Gerald R. Morris, Khalid H. Abed
Mapping a Jacobi Iterative Solver onto a High-Performance Heterogeneous Computer. IEEE Trans. Parallel Distributed Syst. 24 (1) (2013)
Gerald R. Morris, Khalid H. Abed
Mapping Floating-Point Kernels onto High Performance Reconfigurable Computers. J. Comput. 8 (4) (2013)
Khalid H. Abed, Gerald R. Morris
Improving performance of codes with large/irregular stride memory access patterns via high performance reconfigurable computers. J. Parallel Distributed Comput. 73 (11) (2013)
Justin L. Rice, Khalid H. Abed, Gerald R. Morris
Design Heuristics for Mapping Floating-Point Scientific Computational Kernels onto High Performance Reconfigurable Computers. J. Comput. 4 (6) (2009)
Gerald R. Morris, Viktor K. Prasanna
A pipelined-loop-compatible architecture and algorithm to reduce variable-length sets of floating-point data on a reconfigurable computer. J. Parallel Distributed Comput. 68 (7) (2008)
Gerald R. Morris, Viktor K. Prasanna
Sparse Matrix Computations on Reconfigurable Hardware. Computer 40 (3) (2007)
Ling Zhuo, Gerald R. Morris, Viktor K. Prasanna
High-Performance Reduction Circuits Using Deeply Pipelined Operators on FPGAs. IEEE Trans. Parallel Distributed Syst. 18 (10) (2007)
Gerald R. Morris, Viktor K. Prasanna, Richard D. Anderson
A Hybrid Approach for Mapping Conjugate Gradient onto an FPGA-Augmented Reconfigurable Supercomputer. FCCM (2006)
Gerald R. Morris, Viktor K. Prasanna, Richard D. Anderson
An FPGA-Based Application-Specific Processor for Efficient Reduction of Multiple Variable-Length Floating-Point Data Sets. ASAP (2006)
Gerald R. Morris, Ling Zhuo, Viktor K. Prasanna
High-Performance FPGA-Based General Reduction Methods. FCCM (2005)
Gerald R. Morris, Viktor K. Prasanna
An FPGA-Based Floating-Point Jacobi Iterative Solver. ISPAN (2005)
Ling Zhuo, Gerald R. Morris, Viktor K. Prasanna
Designing Scalable FPGA-Based Reduction Circuits Using Pipelined Floating-Point Cores. IPDPS (2005)