Login / Signup
A pipelined-loop-compatible architecture and algorithm to reduce variable-length sets of floating-point data on a reconfigurable computer.
Gerald R. Morris
Viktor K. Prasanna
Published in:
J. Parallel Distributed Comput. (2008)
Keyphrases
</>
variable length
floating point
dynamic programming
image data
data analysis
hardware implementation
fixed length
floating point arithmetic
high quality
data structure
computational complexity
general purpose
sparse matrices
computer systems
fixed point
low cost
computer vision
image processing