High-Performance Reduction Circuits Using Deeply Pipelined Operators on FPGAs.
Ling ZhuoGerald R. MorrisViktor K. PrasannaPublished in: IEEE Trans. Parallel Distributed Syst. (2007)
Keyphrases
- power reduction
- digital circuits
- high speed
- morphological operators
- reduction method
- circuit design
- delay insensitive
- linear array
- asynchronous circuits
- hardware software
- vlsi circuits
- hardware implementation
- analog vlsi
- neural network
- logic circuits
- decision diagrams
- scientific computing
- power consumption
- parallel architectures
- data intensive
- data flow